Interface and electrical properties of buried InGaAs channel MOSFET with an InP barrier layer and Al2O3/HfO2/Al2O3 gate dielectrics

• DOI: 10.7567/1882-0786/ab5acf
• Publication Date: 2019-11-22T23:15:19Z
• Authors: Yue Li; Yonghe Chen; Tangyou Sun; Fabi Zhang; Mingmin Cao; Qi Li; Tao Fu; Gongli Xiao; Yingbo Liu; Honggang Liu; Haiou Li
• Keywords: 0103 physical sciences; 01 natural sciences

The effects of HfO2-Al2O3 laminate structures on the equivalent oxide thickness (EOT), interface characteristics and leakage current properties are investigated on InP substrates. Ti and HfO2-Al2O3 laminate structures are introduced in the MOS capacitors, which present an approximately 1 nm EOT. Compared with Al2O3/HfO2 laminate structure, Al2O3/HfO2/Al2O3 laminate structure exhibits many advantages in border trap density, interface trap density and gate leakage current on InP substrate. The peak transconductance and drive current of buried InGaAs MOSFETs with 0.8 nm-Al2O3/3 nm-HfO2/0.5 nm-Al2O3 gate dielectric layer are increased by 41% and 38%, respectively, compared to that of the 3 nm-Al2O3 layered one