An Implementation of Pipelined Radix-4 FFT Architecture on FPGAs

• DOI: 10.7763/jocet.2014.v2.100
• Publication Date: 2013-10-29T03:17:31Z
• Authors: Jiang Wang; Leif Arne Ronningen
• Keywords: Radix (gastropod)

Design and functional implementation of a 16-point pipelined FFT architecture is presented.The based on the radix-4 algorithm.By exploiting regularity algorithm, butterfly operation multiplier modules were designed.The adopts four butterflies, pipeline stage optimized to balance processing speed area.It was modeled by VHDL, synthesized in FPGA.By adopting this architecture, data throughput could be 2M/s.It extensible for high point FFT.