A5075013845- Low-power high-performance VLSI design
- Numerical Methods and Algorithms
- Digital Filter Design and Implementation
- Embedded Systems Design Techniques
- VLSI and Analog Circuit Testing
- Blind Source Separation Techniques
- VLSI and FPGA Design Techniques
- Parallel Computing and Optimization Techniques
- Political Philosophy and Ethics
- Advanced Wireless Communication Techniques
- Advanced Data Compression Techniques
Veer Surendra Sai University of Technology
2014-2018
This study presents a generalised architecture for cube operation based on Yavadunam sutra of Vedic mathematics. algorithm converts the large magnitude number into smaller and addition operation. The decimal numbers is extended to binary radix-2 system considering digital platforms. cubic synthesised simulated using Xilinx ISE 14.1 software implemented various Field-programmable gate array devices comparison purpose. Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 cadence tool also used...
This study presents a high-speed signed Vedic multiplier (SVM) architecture using redundant binary (RB) representation in Urdhva Tiryagbhyam (UT) sutra. is the first ever effort towards extension of algorithms to numbers. The proposed solves carry propagation issue UT sutra, as free addition possible RB representation. design coded VHDL and synthesised Xilinx ISE 14.4 various FPGA devices. SVM has better speed performances compared with state-of-the-art conventional well architectures.
Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has be handled using nonstandard hardware blocks. The concept Inverted encoding negative weighted bits (IEN) eliminates need extension and design only predefined NonRedundant (NRB) refers both conventional IEN representations. NRB is also useful considering problem related shifting in Carry Save (CS) a RB number. In this paper, we have proposed two new...
For implementation of a fast arithmetic algorithm and efficient hardware realization, signed digit representation is crucial. Redundant binary (RB) 2's complement number the most widely used technique for number. The drawbacks RB include multi valued logic as well need unconventional blocks. Though notation commonly applicable, it needs further optimization in terms delay area. In this paper we proposed operation using inverted encoding negabits (IEN), where value -1 (0) represented 0 (1)....
Signed digit representation is vital for implementation of fast arithmetic algorithm and efficient hardware realization. Redundant binary (RB) number the most widely used technique signed number. Again RB has ability to provide carry propagation free addition. In this paper we have presented an modified redundant (MRB) adder by revising computational rules first step proposed MRB rule, intermediate sum are obtained in terms conventional (Posibits) inverted encoding Negabits (IEN) replacing...