A5089122872- Particle physics theoretical and experimental studies
- High-Energy Particle Collisions Research
- Particle Detector Development and Performance
- Quantum Chromodynamics and Particle Interactions
- Dark Matter and Cosmic Phenomena
- Cosmology and Gravitation Theories
- Neutrino Physics Research
- Computational Physics and Python Applications
- Distributed and Parallel Computing Systems
- Astrophysics and Cosmic Phenomena
- Radiation Detection and Scintillator Technologies
- Advanced Data Storage Technologies
- Black Holes and Theoretical Physics
- Medical Imaging Techniques and Applications
- Atomic and Subatomic Physics Research
- Big Data Technologies and Applications
- Particle Accelerators and Free-Electron Lasers
- Radiation Effects in Electronics
- Structural Analysis of Composite Materials
- Digital Radiography and Breast Imaging
- Statistical Distribution Estimation and Applications
- Engineering and Materials Science Studies
- Parallel Computing and Optimization Techniques
- Scientific Computing and Data Management
- CCD and CMOS Imaging Sensors
University of Toronto
2020-2024
Istituto Nazionale di Fisica Nucleare, Sezione di Bologna
2016-2024
University of Bologna
2016-2024
University of Geneva
2023-2024
Osservatorio astronomico di Bologna
2017-2023
Northern Illinois University
2017-2023
The University of Adelaide
2017-2023
University of Chinese Academy of Sciences
2019-2020
University of Sussex
2019
Istituto Nazionale di Fisica Nucleare
2018-2019
Effects of Single Event Upsets (SEU) and Transients (SET) are studied in the FE-I4B chip innermost layer ATLAS pixel system. SEU/SET affect Global Registers as well settings for individual pixels, causing, among other things, occupancy losses, drops low voltage currents, noisy silent pixels. Quantitative data analysis simulations indicate that SET dominate over SEU on load line memory. Operational issues mitigation techniques presented.
The incoming and future upgrades of LHC will require better performance by the data acquisition system, especially in terms throughput due to higher luminosity that is expected. For this reason, during first shutdown collider 2013/14, ATLAS Pixel Detector has been equipped with a fourth layer— Insertable B-Layer or IBL—located at radius smaller than present three layers. To read out new layer pixels, pixel size respect other outer layers, front end ASIC (FE-I4) was designed as well...
The increase of luminosity in the LHC accelerator at CERN constitutes a challenge for data readout since rate to be transmitted depends on both pileup and trigger frequency. In ATLAS experiment, effect increased is most evident Pixel Detector, which detector closest beam pipe. order face difficult experimental challenges, system was upgraded during last few years. main purpose upgrade provide higher bandwidth by exploiting more recent technologies. new composed two paired electronic boards...
This paper intends to briefly overview the new technological updates on large hadron collider (LHC) A Toroidal LHC ApparatuS (ATLAS) acquisition system of Pixel Detector. The herein presented Read-Out Driver (ROD) is a Versa Module Europa (VME) board devoted data processing, configuration, and control. It designed provide formatting, front-end specific error handling, calibration. was initially interface sensed by insertable B-layer (IBL) with ATLAS Trigger Data AcQuisition (TDAQ). IBL...
The Peripheral Component Interconnect Express (PCIe) Luminosity UPgrade board ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pi $ </tex-math></inline-formula> LUP) was designed by INFN and University of Bologna as a readout interface candidate to be used after the Phase-II upgrade Pixel Detector ATLAS CMS experiments at Large Hadron Collider (LHC). same team in is also responsible for design...
During the next years a great number of laboratories all around world will be involved in upgrading main experiments at CERN’s LHC (ATLAS, CMS, LHCb, ALICE). The ATLAS Bologna group, which collaborates with Pixel Detector DAQ, last two has developed prototype new board named PILUP (PIxel detector high Luminosity UPgrade); this is candidate for redesign DAQ required High project. characteristics are embedded processor (dual-core ARM) and large communication bandwidth (up to 60 Gb/s through...
Hog (HDL on Git) is an open-source tool designed to manage Git-based HDL repositories. It aims simplify project development, maintenance, and versioning by using Git guarantee synthesis implementation reproducibility binary file traceability. This ensured linking each produced a specific commit, embedding the commit hash (SHA) into via generics stored in firmware registers. released twice year, January June. We present here latest stable version 2023.1, which introduces major novel features,...
After having designed and commissioned the readout electronics currently implemented in Insertable B-Layer, Layer 1 2 of ATLAS Pixel Detector (B-Layer Disk is under commissioning), we have a new electronic board looking primarily at upgrade LHC Detectors. Two prototypes PCI Express board, namely Pixel_ROD, featuring all minimal input-outputs interfaces to address future front-end electronics, already been fabricated tested. The digital protocols used for GBTx RD53A chips investigated able...