A5007953332- Radiation Effects in Electronics
- VLSI and Analog Circuit Testing
- Physical Unclonable Functions (PUFs) and Hardware Security
- Cryptographic Implementations and Security
- Security and Verification in Computing
- Integrated Circuits and Semiconductor Failure Analysis
- Embedded Systems Design Techniques
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Distributed systems and fault tolerance
- Advanced Malware Detection Techniques
- Software Reliability and Analysis Research
- VLSI and FPGA Design Techniques
- Cryptography and Residue Arithmetic
- Formal Methods in Verification
- Cryptography and Data Security
- Electrostatic Discharge in Electronics
- Chaos-based Image/Signal Encryption
- Parallel Computing and Optimization Techniques
- Advancements in Photolithography Techniques
- Coding theory and cryptography
- Software Testing and Debugging Techniques
- Interconnection Networks and Systems
- Quantum-Dot Cellular Automata
- Fault Detection and Control Systems
Université Grenoble Alpes
2015-2025
Institut polytechnique de Grenoble
2012-2025
Centre National de la Recherche Scientifique
2015-2025
Techniques of Informatics and Microelectronics for Integrated Systems Architecture
2013-2023
Université Joseph Fourier
2009-2013
Centre Interuniversitaire de MicroElectronique et Nanotechnologies
1998
Institut National Polytechnique de Toulouse
1995
This paper examines aspects of design technology required to explore advanced logic-circuit using carbon nanotube field-effect transistor (CNTFET) devices. An overview current types CNTFETs is given and highlights the salient characteristics each. Compact modeling issues are addressed new models proposed implementing: 1) a physics-based calculation energy conduction sub-band minima allow realistic analysis impact CNT helicity radius on dc characteristics; 2) descriptions ambipolar behavior...
Analyzing at an early stage of the design potential faulty behaviors a circuit becomes major concern due to increasing probability faults. It is proposed carry out such analysis using fault injections in RT-level VHDL descriptions and hardware prototyping under design. Injection erroneous transitions automated results are presented.
A method for introducing online test facilities in a controller with very low overhead is presented. This consists of detecting illegal paths the control flow graph. These may be due either to permanent faults or transient errors. The state code compacted through polynomial division. An implicit justifying signature applied at level and ensures identical signatures before each join mode are then independent path followed previously graph, comparison reference data greatly facilitated....
S. Skorobogatov and R. Anderson identified laser illumination as an effective technique to conduct fault attacks in 2002. In these early days of laser-induced injection, it was proven be possible inject single-bit faults into integrated circuits. This corresponds the more restrictive model found attack bibliography. The target area under (a few micrometers, down ~1 µm) broadly matched that a single transistor. It consistent with model. However, since then technology secure devices has...
This paper presents hardening techniques against fault attacks and the practical evaluation of their efficiency. The circuit technology investigated to improve resistance is asynchronous logic. Specific properties circuits make them inherently resistant a large class faults. An analysis behavior in presence faults shows that they are an interesting alternative design robust systems. A diagnosis enables us propose tolerance resistance. They applied at time aim exploiting quasi-delay...
This paper presents a transient faults sensitivity evaluation for Quasi Delay Insensitive (QDI) asynchronous circuits. Because of their specific architecture, circuits have very different behavior than synchronous in the presence faults. We address effects QDI and describe causes that lead to be memorized into one or more soft errors. Therefore, refined fault criterion is defined this class methodology enables us point out weak parts circuit. An analysis tool implemented support evaluation....
Side-channel analysis is one of the most efficient techniques available to an attacker break security a cryptographic device. Started as monitoring computation time or power, it has evolved into considering several other possible information leakage sources, such electromagnetic (EM) emissions. EM waves can be very attractive means attack implementation: they are contactless, and their intrinsic spatial, temporal, frequency source richer than power consumption. Existing countermeasures may...
Fully Homomorphic Encryption (FHE) becomes an important encryption scheme in the frame of Cloud computing. Current software implementations are however very slow and require a huge computing power. This work investigates possibility to accelerate FHE by implementing it off-the-shelf FPGAs. The focus is on one critical function scheme: polynomial multiplication. In this paper, three algorithms considered optimized architecture proposed for each them. major contribution paper comparison...
Control flow checking techniques are discussed. Invariant properties of the control can be checked at two different levels: verification sequencing in controller microprocessor or application program. has been implemented, levels, versions a 32-b designed CMOS 1.5- mu technology. Integration monitors on silicon is detailed. The overhead due to online test devices precisely Different this have and implemented order make real cost comparisons components with identical functionality but...
Due to their complex architecture, the radiation sensitivity of general-purpose processors is intrinsically linked software that executed. In order obtain a consistent assessment fault tolerance during experiments, it necessary have representative final application. For this purpose, we are developing methodology based on application profiling tool allows us detailed view use hardware resources according profile. This analysis flow has been applied reduced instruction set computer (RISC-V)...
This paper reviews the main approaches used to evaluate effect of single event transients and upsets in digital circuits described at different abstraction levels. The two fault models are first discussed with respect circuit description levels, then complementary dependability evaluation methods summarized.
Lasers have become one of the most efficient means to attack secure integrated systems. Actual faults or errors induced in system depend on many parameters, including circuit technology and laser characteristics. Understanding physical effects is mandatory correctly evaluate during design flow potential consequences a laser-based implement counter-measures. This paper presents results obtained within LIESSE project, aiming at defining comprehensive approach for designers. Outcomes include...
This paper presents practical results on the evaluation of fault countermeasures implemented in an asynchronous DES coprocessor. The theory underlying was previously published IOLTS 2005. For first time this work reports a applied ASICs. Two crypto processors were fabricated using 130 nm STmicroelectronics CMOS process; one as reference and hardened specific technique. enables us to compare resistance both circuits against injection validate proposed countermeasures. set-up injection, laser,...
Evaluating early at design time the level of security achieved with respect to fault-based hardware attacks requires understanding and accurately modeling faults that can actually occur in a circuit under attack. Attacks lasers produce single or multiple-bit errors, while having local impact circuit. This paper discusses several fault error models be considered summarizes experimental results providing some insights into consequences model chosen for evaluation.
A hierarchical test generation method is presented which based on a functional approach to guide backward and forward propagations. The proposed algorithm permits solving most propagation conflicts by taking advantage of the functionality implemented block avoids costly unnecessary design modifications. It has been its effectiveness proved set datapaths. formalism algorithms are general enough handle any type synchronous digital circuit.
Ring Oscillators (ROs) are essential building blocks in digital devices used for instance clock generation, True Random Number Generators (TRNGs), Physical Unclonable Functions (PUFs) or on-chip voltage temperature sensors. Their response to laser pulses, EM (ElectroMagnetic) harmonic fault injections radio frequency interferences injected into the power distribution network has already been extensively studied. In this paper, we present experimental characterization results of pulsed...
AI systems have an increasing sprawling impact in many application areas. Embedded built on strong conflictual implementation constraints, including high computation speed, low power consumption, energy efficiency, robustness and cost. Neural Networks (NNs) used by these are intrinsically partially tolerant to disturbances. As a consequence, they interesting target for approximate computing seeking reduced resources, lower consumption faster computation. Also, the large number of...