A5042040286- Parallel Computing and Optimization Techniques
- Interconnection Networks and Systems
- Advanced Memory and Neural Computing
- Advanced Data Storage Technologies
- 3D IC and TSV technologies
- Phase-change materials and chalcogenides
- Blood transfusion and management
- Network Packet Processing and Optimization
- Trauma and Emergency Care Studies
- Embedded Systems Design Techniques
- Patient Safety and Medication Errors
- Trauma, Hemostasis, Coagulopathy, Resuscitation
- Pharmaceutical Practices and Patient Outcomes
- Emergency and Acute Care Studies
- Image Enhancement Techniques
- Distributed and Parallel Computing Systems
- Advanced Image and Video Retrieval Techniques
- Ferroelectric and Negative Capacitance Devices
- Video Surveillance and Tracking Methods
Advanced Micro Devices (United States)
2023
The Ohio State University Wexner Medical Center
2022
Allegheny Health Network
2022
Advanced Micro Devices (Canada)
2016-2018
University of Toronto
2018
Pennsylvania State University
2010-2016
In this letter, a flexible memory simulator - NVMain 2.0, is introduced to help the community for modeling not only commodity DRAMs but also emerging technologies, such as die-stacked DRAM caches, non-volatile memories (e.g., STT-RAM, PCRAM, and ReRAM) including multi-level cells (MLC), hybrid plus systems. Compared existing simulators, 2.0 features user interface with compelling simulation speed capability of providing sub-array-level parallelism, fine-grained refresh, MLC data encoder...
System-on-Chip (SoC) complexity and the increasing costs of silicon motivate breaking an SoC into smaller "chiplets." A chiplet-based design process has promise to enable fast construction by using advanced packaging technologies tightly integrate multiple disparate chips (e.g., CPU, GPU, memory, FPGA). However, when assembling chiplets a single SoC, correctness validation becomes significant challenge. In particular, network-on-chip (NoC) used within individual across tie them together can...
The challenges to push computing exaflop levels are difficult given desired targets for memory capacity, bandwidth, power efficiency, reliability, and cost. This paper presents a vision an architecture that can be used construct exascale systems. We describe conceptual Exascale Node Architecture (ENA), which is the computational building block supercomputer. ENA consists of Heterogeneous Processor (EHP) coupled with advanced system. EHP provides high-performance accelerated processing unit...
Modern GPU frameworks use a two-phase compilation approach. Kernels written in high-level language are initially compiled to an implementation agnostic intermediate (IL), then finalized the machine ISA only when target hardware is known. Most microarchitecture simulators available academics execute IL instructions because there substantially less functional state associated with instructions, and some situations, ISA's intellectual property may not be publicly disclosed. In this paper, we...
In recent 3DIC studies, through silicon vias (TSV) are usually employed as the vertical interconnects in 3D stack. Despite its benefit of short latency and low power, forming TSVs adds additional complexities to fabrication process. Recently, inductive/capactive-coupling links proposed replace stacking because them lower. Although state-of-the-art inductive/capacitive-coupling show comparable bandwidth power TSV, relatively large footprints those compromise their area efficiencies. this...
In recent 3DIC studies, through silicon vias (TSV) are usually employed as the vertical interconnects in 3D stack. Despite its benefit of short latency and low power, forming TSVs adds additional complexities to fabrication process. Recently, inductive/capactive-coupling links proposed replace stacking because them lower. Although state-of-the-art inductive/capacitive-coupling show comparable bandwidth power TSV, relatively large footprints those compromise their area efficiencies. this...
High-performance computing, enterprise, and datacenter servers are driving demands for higher total memory capacity as well performance. Memory "cubes" with high per-package (from 3D integration) along high-speed point-to-point interconnects provide a scalable system architecture the potential to deliver both Multiple such cubes connected together can form "Memory Network" (MN), but design space MNs is quite vast, including multiple topology types technologies per cube.
The interconnect or network on chip (NoC) is an increasingly important component in processors. As systems scale up size and functionality, the ability to efficiently model larger more complex NoCs becomes design evaluation of such systems. Recent work proposed "SynFull" methodology that performs statistical analysis a workload's NoC traffic create compact generators based Markov models. While models generate synthetic traffic, statistically similar original trace can be used for fast...
Background subtraction is an important problem in computer vision and a fundamental task for many applications. In the past, background has been limited by amount of computing power available. The was performed on small frames and, case adaptive algorithms, with relatively models to achieve real-time performance. With introduction multi- many-core chip-multiprocessors (CMP), more resources are available handle this task. advent specialized CMP, such as NVIDIA's Compute Unified Device...
Energy becomes the primary concern in nowadays multi-core architecture designs. Moore's law predicts that exponentially increasing number of cores can be packed into a single chip every two years, however, power density is obstacle to continuous performance gains. Recent studies show heterogeneous competitive promising solution optimize per watt. In this paper, different types are discussed. For each type, current challenges and latest solutions briefly introduced. Preliminary analyses...
Emerging memory technologies such as phase-change (PCM) and resistive RAMs (RRAM) have been proposed promising candidates for future DRAM replacements. Due to the nature of how these memories operate, unique properties (such non-destructive read current-sensing) can be exploited further subdivide provide increasing parallelism with negligible overhead. In this work, we leverage design a finegrained non-volatile (FgNVM), featuring two-dimensional bank subdivision tile-level (TLP) in NVM bank,...
High-performance computing, enterprise, and datacenter servers are driving demands for higher total memory capacity as well performance. Memory "cubes" with high per-package (from 3D integration) along high-speed point-to-point interconnects provide a scalable system architecture the potential to deliver both Multiple such cubes connected together can form "Memory Network" (MN), but design space MNs is quite vast, including multiple topology types technologies per cube. In this work, we...
The pace of advancement the top-end supercomputers historically followed an exponential curve similar to (and driven in part by) Moore's Law. Shortly after hitting petaflop mark, community started looking ahead next milestone: Exascale. However, many obstacles were already looming on horizon, such as slowing Law, and others like end Dennard Scaling had arrived. Anticipating significant challenges for overall high-performance computing (HPC) achieve 1000x improvement, U.S. Department Energy...
The purpose of this study was to evaluate the cost avoidance associated with emergency medicine pharmacist (EMP) presence in department (ED) using a novel framework.This single-center, retrospective, observational examined EMP interventions from November 1, 2021, through March 31, 2022. EMPs prospectively selected up 10 shifts which log during period. Interventions were categorized into 25 categories, incorporated recently proposed probability variables. All categories organized 4 broad...