In this work, we investigate for the first time impact of Negative Capacitance FinFET (NC-FinFET) technology on performance processors under effects process variations various operating voltages. The industry compact model FinFETs (BSIM-CMG) is fully calibrated to reproduce Intel 14nm data high volume manufacturing process. A physics-based negative capacitance (NC) integrated and solved self-consistently within BSIM-CMG model. This allows creation NC-FinFET standard cell libraries, while...

To ensure the correct functionality of a chip throughout its entire lifetime, preliminary circuit analysis with respect to aging-induced degradation is indispensable. However, state-of-the-art techniques only allow for consideration uniformly applied degradations, despite fact that different workloads will lead degradations due their distinct induced activities. This imposes over-pessimism when estimating required timing guardbands, resulting in an unnecessary loss performance and...

Aging-induced degradation imposes a major challenge to the designer when estimating timing guardbands. This problem increases as traditional worst-case corners bring over-pessimism designers, exacerbating competitive and close-to-the-edge designs. In this work, we present an accurate machine learning approach for aging-aware cell library characterization, enabling evaluate their circuit under impact of precisely selected degradation. Unlike state art, characterization designer, empowering...

Process variations and device aging impose profound challenges for circuit designers. Without a precise understanding of the impact on delay paths, guardbands, which keep timing violations at bay, cannot be correctly estimated. This problem is exacerbated advanced technology nodes, where transistor dimensions reach atomic levels established margins are severely constrained. Hence, traditional worst-case analysis becomes impractical, resulting in intolerable performance overheads. Contrarily,...

Machine learning (ML)-driven standard cell library characterization enables rapid, on-the-fly generation of libraries, opening the door for extensive design-space exploration and other, previously infeasible approaches. However, benefits ML-based are strongly limited by its high demand in training data costly SPICE simulation required to generate samples. Therefore, efficient strategies needed minimize ML models while still sustaining prediction accuracy. In this work, we explore multiple...

Quantum computing can enable novel algorithms infeasible for classical computers. For example, new material synthesis and drug optimization could benefit if quantum computers offered more (qubit). One obstacle scaling up is the connection between their cryogenic qubits at temperatures a few millikelvin kelvin (depending on qubit type) processing system chip (soc) room temperature (300K). Through this connection, outside heat leaks to disrupt state. Hence, moving SoC into part eliminates...

To explore the full potential of any circuit and ensure its functionality at run-time, cell libraries beyond typical PVT corners are needed. This holds even more for emerging technologies like Negative Capacitance (NC)-FinFET, where research in finding optimal set transistor parameters is still infancy. Design Technology Co-Optimization (DTCO) tackles bridging large existing gap between device physics figures merit circuits. In this paper, we propose a Machine Learning (ML) approach to...

In this work, we are the first to demonstrate how well-established EDA tool flows can be employed upheave Self- Heating Effects (SHE) from individual devices at transistor level all way up complete large circuits final layout (i.e., GDS-II) level. Transistor SHE imposes an ever-growing reliability challenge due continuous shrinking of geometries alongside non-ideal voltage scaling in advanced technology nodes. The is largely exacerbated when more confined 3D structures adopted build...

Compact models of transistors act as the link between semiconductor technology and circuit design via simulations. Unfortunately, compact model development calibration is a challenging time-intensive task, hindering rapid prototyping (via simulations) in emerging technologies. Moreover, foundries want to protect their confidential details prevent reverse engineering. Hence, they limit access transistor commercial technologies (e.g., with Non-Disclosure-Agreements). In this work, we propose...

With the continuous scaling in technology nodes, transistor self-heating effect (SHE) emerges as a growing threat to circuit reliability. Increasingly confined structures and advanced materials exacerbate thermal insulation, concealing temperature hotspots transistor's channel. Without consideration of these increased temperatures, reliability effects such aging will be underestimated, putting at risk. In this work, we propose novel design flow that enables designers extract accurate SHE...

Small Delay Faults (SDFs) introduce additional delays smaller than the capture time and require timing-aware test pattern generation. Since process variations can invalidate effectiveness of such patterns, different circuit instances may show a fault coverage for same set. This paper presents method to generate sets SDFs which are valid all timings. The overcomes limitations known Automatic Test Pattern Generation (ATPG) has use sampling under due computational complexity. A statistical...

Logic Built-In Self-Test (LBIST) with stored deterministic patterns is supported by the major CAD vendors and gaining increasing attention, especially for safety-critical applications such as automotive. It used both manufacturing periodic in-field testing. An unresolved challenge so far stems from inevitable process variations. This paper presents first approach storage-based BIST addressing delay faults under variations multiple voltages. A unified solution pattern generation, test set...

Circuit analysis with respect to aging-induced degradation is critical ensure correct operation throughout the entire lifetime of a chip. However, state-of-the-art techniques only allow for consideration uniformly applied degradation, despite fact that different workloads will lead degradations due induced activities. This imposes over-pessimism in estimating required timing guardbands, resulting unnecessary losses performance and efficiency. In this work, we propose an approach takes...

Recent breakthroughs in Neural Networks (NNs) led to significant accuracy improvements of several machine learning applications such as image classification and voice recognition. However, this improvement comes at the cost an immense increase computation demands. NNs became one most common computationally intensive workloads today's datacenters. To address these computational demands, Google announced 2016 Tensor Processing Unit (TPU), advanced custom ASIC accelerator for NN inference. Two...

Cryogenic CMOS circuits operate at temperatures close to absolute zero and are essential in many applications such as controllers for quantum computing but also medical engineering, space technology, or physical instruments. However, operating cryogenic fundamentally changes the underlying semiconductor physics that governs transistor—rendering existing design automation approaches infeasible. In this work, we propose implement first end-to-end approach enables circuits. To end, (1) perform...

Graph Neural Networks (GNNs) are one of the best-performing models for processing graph data. They known to have considerable computational complexity, despite smaller number parameters compared traditional Deep (DNNs). Operations-to-parameters ratio GNNs can be tens and hundreds times higher than DNNs, depending on input size. This complexity indicates importance arithmetic operation optimization within through model quantization approximation. In this work, first time, we combine both...

<p>Graph Neural Networks (GNNs) are one of the best-performing models for processing graph data. They known to have considerable computational complexity, despite smaller number parameters compared traditional Deep (DNNs). Operations-to-parameters ratio GNNs can be tens and hundreds times higher than DNNs, depending on input size. This complexity indicates importance arithmetic operation optimization within through model quantization approximation. In this work, first time, we combine...

Adaptive Voltage Frequency Scaling (AVFS) is an important means to overcome process-induced variability challenges for advanced high-performance circuits. AVFS requires and allows determining the maximum speed F <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> (V xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> ) reachable under a set of certain operation voltages V . In this paper, it shown that measurements contain relevant data...

Process variations and device aging impose profound challenges for circuit designers. Without a precise understanding of the impact on delay paths, guardbands, which keep timing violations at bay, cannot be correctly estimated. This problem is exacerbated advanced technology nodes, where transistor dimensions reach atomic levels established margins are severely constrained. Hence, traditional worst-case analysis becomes impractical, resulting in intolerable performance overheads. Contrarily,...

Cryogenic CMOS devices face the challenge of excessive self-heating (SH), which has emerged as a major concern for quantum computing (QC). This work is first to reveal impact SH in cryogenic circuits, from transistor level all way up processor level, using 28nm FDSOI technology. The heat generated interfacing circuits severely hinders lifetime qubits, are thermal noise-sensitive. To investigate on we extend industry-standard BSIM-IMG model incorporate physics-based temperature-specific...

With increasingly confined 3D structures and newly-adopted materials of higher thermal resistance, transistor self-heating has risen to a critical reliability threat in state-of-the-art emerging process nodes. One the challenges is accelerated aging, which leads earlier failure chip if not considered appropriately. Nevertheless, adequate consideration aging effects, induced by self-heating, throughout large circuit design profoundly challenging due gap between where does originate (i.e., at...

&lt;p&gt;Quantum computing can enable novel algorithms infeasible for classical computers. For example, new material synthesis and drug optimization could benefit if quantum computers offered more bits (qubits). One obstacle scaling up is the connection between their cryogenic qubits at a few (milli)kelvin traditional processing system on chip (SoC) room temperature ( 300 K). Through this connection, outside heat leaks to disrupt state. Hence, moving SoC into part eliminates leakage....