This paper describes an all-digital PVT-variation tolerant true-random number generator (TRNG), fabricated in 45 nm high-k/metal-gate CMOS, targeted for on-die entropy generation high-performance microprocessors. The TRNG harvests differential thermal-noise at the diffusion nodes of a pre-charged cross-coupled inverter pair to resolve out metastability, generating one random bit/cycle. A self-calibrating 2-step tuning mechanism using coarse-grained configurable inverters and fine-grained...

Field-Programmable Gate Arrays (FPGAs) have been aggressively moving to lower gate length technologies. Such a scaling of technology has an adverse impact on the reliability underlying circuits in such architectures. Various different physical phenomena recently explored and demonstrated form both transient error susceptibility permanent failures. In this work, we analyze two types hard errors, namely, Time- Dependent Dielectric Breakdown (TDDB) Electromigration (EM) FPGAs. We also study...

An all-digital True Random Number Generator is fabricated in 45nm CMOS with 2.4Gbps random bit throughput and total power consumption of 7mW. Two-step coarse/fine-grained tuning a self-calibrating feedback loop enables robust operation the presence 20% process variation while providing immunity to run-time voltage temperature fluctuations. The 100% digital design compact layout occupying 4004μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

Soft errors that change configuration bits of an SRAM based FPGA modify the functionality design. The proliferation devices in various critical applications makes it important to increase their immunity soft errors. In this work, we propose use asymmetric (ASRAM) structure is optimized for error and leakage when storing a preferred value. key our approach observation bitstream composed 87% zeros across different designs. Consequently, ASRAM cell zero (ASRAM-0) reduces failure time by 25% as...

The focus of the paper is on renewable energy-based rural electrification system. Two concepts have been used in finding solutions to issues related this micro-grid first best fitted model hybrid configuration system, which utilizes village-owned resources, such as abundant biomass and solar irradiation. second that observed improved performance terms system sizing, techno-economic performance, environmental stability over different power storage backup media. practical aspects suggestion...

The integration of SNOMED CT into the Unified Medical Language System (UMLS) involved alignment two views synonymy that were different because vocabulary systems have intended purposes and editing principles. UMLS is organized according to one view synonymy, but its structure also represents all individual present in source vocabularies. Despite progress knowledge-based automation development maintenance vocabularies, manual curation still main method determining synonymy. aim this study was...

Aggressive scaling of technology has an adverse impact on the reliability VLSI circuits. Apart from increasing transient error susceptibility, circuits also become more vulnerable to permanent damage and failures due different physical phenomenon. Such concerns have been recently demonstrated for regular micro-architectures. In this work we demonstrate vulnerability field programmable gate arrays (FPGA)s two types hard errors, namely, time dependent dielectric breakdown (TDDB)...

This paper describes an all-digital on-die true random number generator implemented in 45 nm CMOS technology, with bit throughput of 4 Gbps and total energy consumption 0.57 pJ/bit. A 2-step tuning mechanism enables robust operation the presence up to 20% fabrication-time process variation as well immunity run-time voltage temperature fluctuation. The 100% use digital components a compact layout occupying 1024 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

A 32 nm on-die fine-grained reconfigurable fabric for DSP/media accelerators is fabricated and occupies a 0.076 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die. The optimized hybrid arithmetic configurable logic blocks with self-decoded look-up tables, ultra-low voltage PVT-tolerant register file circuits dual-supply operation help enable 2.4 GHz nominal performance at 1.0 V 320 mV-to-1.2 dynamic range. peak energy efficiency...

This paper mainly deals with the optimum design and performance of hybrid renewable electrification system for remote villages southern part India. Constructed simulated a energy (HRE) system, which was consists fully village owned resources such as solar, wind biomass energies. Through this case study typical Indian load demand wants to meet out by suitable configuration least investment. The proposed system's technical ensuring highest fraction annual unmet percentage. economical...

The growing Indian economy calls for the urgent need to review ways and means conserve energy consumed by industrial sector. As a part of fulfilling objective, Government India has made it mandatory conduct periodic audits in bulk sector be followed up with practical implementation conservation (ECON) measures as suggested audit team. This paper presents conducted medium-size textile mill western Tamil Nadu India. been conducted, an exhaustive study consumption pattern carried out using...

This research paper investigates optimal tuning of PID co-efficients using the Tree-Seed Algorithm. A DC motor drive with a controller is considered simulation example. The step response algorithm-based compared Ziegler Nichols (closed-loop) method and Skogestad Internal Model Control. In this research, Disk-based margins are proposed to investigate feedback loop for robust stability against gain phase uncertainty (i.e open-loop increased or decreased by 50%, ± 270) various values skew, σ....

As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the is expended unused multiplexers used interconnect fabric. This work focuses on these by controlling their inputs. We investigate issues involved implementing such a technique and also show experimental results demonstrating effectiveness our approach.

Design, modeling, and characterization of inductors embedded in a package substrate promising higher quality factor (Q) lower cost than on-chip is described. In addition to the problem large conductor losses, on-die with or without magnetic materials consume considerable die area require removal first-level interconnect bumps beneath them maintain reasonably high Q value. Moving eliminates need for bump array depopulation and, thus, mitigates potential reliability problems caused by voids...

Aggressive scaling of technology has an adverse impact on the reliability VLSI circuits. Apart from increasing transient error susceptibility, circuits also become more vulnerable to permanent damage and failures due different physical phenomenon. Such concerns have been recently demonstrated for regular micro-architectures. In this work we demonstrate vulnerability Field Programmable Gate Arrays (FPGA)s two types hard errors, namely, Time Dependent Dielectric Breakdown (TDDB)...