Verifying the robustness property of a general Rectified Linear Unit (ReLU) network is an NP-complete problem [Katz, Barrett, Dill, Julian and Kochenderfer CAV17]. Although finding exact minimum adversarial distortion hard, giving certified lower bound possible. Current available methods computing such are either time-consuming or delivering low quality bounds that too loose to be useful. In this paper, we exploit special structure ReLU networks provide two computationally efficient...

Variation is a key concern in semiconductor manufacturing and manifest several forms. Spatial variation across each wafer results from equipment or process limitations, within die may be exacerbated further by complex pattern dependencies. information important not only for optimization control, but also design of circuits that are robust to such variation. Systematic random components the must identified, models relating spatial specific causes needed. In this work, extraction modeling...

Training neural networks with verifiable robustness guarantees is challenging. Several existing approaches utilize linear relaxation based network output bounds under perturbation, but they can slow down training by a factor of hundreds depending on the underlying architectures. Meanwhile, interval bound propagation (IBP) efficient and significantly outperforms methods many tasks, yet it may suffer from stability issues since are much looser especially at beginning training. In this paper,...

A deep reinforcement learning (DRL) agent observes its states through observations, which may contain natural measurement errors or adversarial noises. Since the observations deviate from true states, they can mislead into making suboptimal actions. Several works have shown this vulnerability via attacks, but existing approaches on improving robustness of DRL under setting limited success and lack for theoretical principles. We show that naively applying techniques classification tasks, like...

In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing ILD variation. We present generalizable methodology selecting an optimal metal-fill practice with goal of satisfying given specification while minimizing added interconnect capacitance associated patterning. Data from two...

Pattern-dependent effects are a key concern in chemical-mechanical polishing (CMP) processes. In oxide CMP, variation the interlevel dielectric (ILD) thickness across each die and wafer can impact circuit performance reduce yield. this work, we present new test mask designs associated measurement analysis methods to efficiently characterize model behavior as function of layout pattern factors-specifically area, density, pitch, perimeter/area effects. An important goal approach is rapid...

Chemical-mechanical polishing (CMP) has emerged as the dominant dielectric planarization method due to its ability reduce topography over longer lateral distances than earlier techniques. However, CMP still suffers from pattern dependencies that result in large variation polished oxide thickness across typical chips, which can impact circuit performance and yield. A comprehensive semiphysical dependent model of process, integrated with a parameter extraction process characterization...

The adversarial training procedure proposed by Madry et al. (2018) is one of the most effective methods to defend against examples in deep neural networks (DNNs). In our paper, we shed some lights on practicality and hardness showing that effectiveness (robustness test set) has a strong correlation with distance between point manifold data embedded network. Test are relatively far away from this more likely be vulnerable attacks. Consequentially, an based defense susceptible new class...

We study the robustness of reinforcement learning (RL) with adversarially perturbed state observations, which aligns setting many adversarial attacks to deep (DRL) and is also important for rolling out real-world RL agent under unpredictable sensing noise. With a fixed policy, we demonstrate that an optimal adversary perturb observations can be found, guaranteed obtain worst case reward. For DRL settings, this leads novel empirical attack agents via learned much stronger than previous ones....

In this review, recent trends in microelectronics packaging reliability are summarized. We review the technology from early concepts, including wire bond and BGA, to advanced techniques used HI schemes such as 3D stacking, interposers, fan-out packaging, more recently developed silicon interconnect fabric integration. This includes approaches for both design modification studies packaged device validation. Methods explored compatibility new complex assemblies. Suggestions proposed...

We present a methodology to study the impact of spatial pattern dependent variation on circuit performance and implement technique in CAD framework. investigate effects interconnect CMP poly CD device delay clock skew both aluminum copper technology. Our results indicate that strongly affects delay, while has large 1 GHz design. Given this impact, tools future must account for such systematic within-die variations.

Quantum computing is among the most promising emerging techniques to solve problems that are computationally intractable on classical hardware. A large body of existing works focus using variational quantum algorithms gate level for machine learning tasks, such as circuit (VQC). However, VQC has limited flexibility and expressibility due number parameters, e.g. only one parameter can be trained in rotation gate. On other hand, we observe pulses lower than gates stack offers more control...

A prototype hardware/software system has been developed and applied to the control of single wafer chemical-mechanical polishing (CMP) processes. The methodology consists experimental design build response surface linearized models process, use feedback change recipe parameters (machine settings) on a lot by basis. Acceptable regression were constructed for average removal rate nonuniformity, which are calculated based film thickness measurement at nine points 8" blanket oxide wafers. For...

A prototype hardware/software system has been developed and applied to the control of single wafer chemical-mechanical polishing (CMP) processes. The methodology consists experimental design build response surface linearized models process, use feedback change recipe parameters (machine settings) on a lot by basis. Acceptable regression for tool process were constructed average removal rate nonuniformity which are calculated based film thickness measurement at nine points 8-in blanket oxide...

Rapid modeling and optimization of manufacturing processes, devices, circuits are required to support modern integrated circuit technology development yield improvement. We have prototyped applied an system, called DOE/Opt, for performing Design Experiments (DOE), Response Surface Modeling (RSM), Optimization (Opt). The system be modeled optimized can either physical or simulation based. Within the DOE/Opt coupling external experimental tools is achieved via embedded extension language based...

A 12-bit 50MS/s SAR ADC implemented in 65nm CMOS technology is presented. The design employs redundancy to relax the DAC settling requirement and provide sufficient room for errors such that static nonlinearity caused by capacitor mismatches can be digitally removed. incorporated into using a tri-level switching scheme our modified split-capacitor array achieve highest efficiency while still preserving symmetry error tolerance. new code-density based digital background calibration algorithm...

Although adversarial examples and model robustness have been extensively studied in the context of linear models neural networks, research on this issue tree-based how to make robust against is still limited. In paper, we show that tree based are also vulnerable develop a novel algorithm learn trees. At its core, our method aims optimize performance under worst-case perturbation input features, which leads max-min saddle point problem. Incorporating objective into decision building procedure...

With the continuous drive toward integrated circuits scaling, efficient yield analysis is becoming more crucial yet challenging. In this paper, we propose a novel methodology for wafer map defect pattern classification using deep selective learning. Our proposed approach features an reject option where model chooses to abstain from predicting class label when misclassification risk high. Thus, providing trade-off between prediction coverage and risk. This learning scheme allows new...

This paper contributes the first study of manufacturing variation on interconnect timing performance in a high speed microprocessor. Also new this is methodology using analysis conjunction with post-extraction net adjustment to account for structure (e.g., that arising due pattern dependencies); efficient enough enable thousands nets be analyzed and compatible current CAD tools.

We present a one-class anomaly detection method that uses time series sensor data to detect anomalies or faults in semiconductor fabrication processes. Critically, this is trained using only small amounts of known successful run data, making it possible implement for many processes and recipes without needing example faults. The proposed kernel density estimation (KDE) create probability distributions values during nominal processing. When classifying unseen we determine the likelihood arose...

Guidance techniques are simple yet effective for improving conditional generation in diffusion models. Albeit their empirical success, the practical implementation of guidance diverges significantly from its theoretical motivation. In this paper, we reconcile discrepancy by replacing scaled marginal distribution target, which prove theoretically invalid, with a valid joint objective. Additionally, show that established implementations approximations to intractable optimal solution under no...