A5040502545- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Advancements in Semiconductor Devices and Circuit Design
- Copper Interconnects and Reliability
- Aluminum Alloy Microstructure Properties
- Intermetallics and Advanced Alloy Properties
- High-Temperature Coating Behaviors
- Optical Coatings and Gratings
- 3D IC and TSV technologies
- Aluminum Alloys Composites Properties
- Electronic Packaging and Soldering Technologies
- Microstructure and mechanical properties
- Advanced Surface Polishing Techniques
- Advanced ceramic materials synthesis
- Catalytic Processes in Materials Science
Semiconductor Manufacturing International (Italy)
2012-2021
Fudan University
2021
Semiconductor Manufacturing International (China)
2015
Beihang University
1990-2007
The optimized postdeposition annealing (PDA) of the high-k metal gate is investigated for 1/f noise performance improvement in FinFET technology by using spike (SPA) and SPA-combined millisecond flash (MFLA) treatment. It demonstrates that additional MFLA can significantly reduce without device degradation. Based on low-frequency analysis, reduced arises from decrease density interface traps (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
32/28nm BEOL Cu CMP process with ultra low k scheme is investigated in the different aspects. Firstly barrier metal (BM) slurry selection proper selectivity most critical part to reduce topography. The topography can be minimized by precisely control BM slurry’s selectivity. Secondly, layout design, such as pattern density, line and space width, has significant impact on WID variation. test results show more correction at dense for thinner where polishing dominate factor. While fat line, it...
Aluminum (Al) film has been implemented in semiconductor manufacturing such as gap fill the metal gate trench. Al-induced crystallization and layer exchange processes showed great impact on grain size, Al size was varied by deposition rate temperature. We investigated of deposited different substrates p-Si, PEOX thermal oxide DC magnetron sputtering. Grain roughness were characterized SEM AFM. The polishing result correlative with smoothness continuous better CMP performance, while larger...
Novel CuCMP slurry was evaluated under different polishing conditions and its impact on topography, thickness in line test performance investigated. Generally, such as dishing erosion, results from over-polishing after Cu step it can be modified reduced by fine tuning process parameters. Firstly, condition has been attempted to produce topography for barrier compensate order cater integration scheme with oxide material. Secondly, due high selectivity is used during polishing. Longer time...
SiGe channel metal oxide semiconductor field effect transistor (MOSFET) became a choice of material as performance booster in leading edge logic technologies. In this study, we demonstrate integration solutions for dual Fin formation (Si nFET, pFET) using buried approach on 300 mm Si wafer. Plasma-induced damage (PID) layer, which thickness ranges from 0.5 nm to 2.5 nm, was observed after trench (p-trench) etch EPI growth. This PID inorganic layer leads dislocation defect. And careful...