A5089148113- CCD and CMOS Imaging Sensors
- Analog and Mixed-Signal Circuit Design
- Advanced Memory and Neural Computing
- Neural Networks and Reservoir Computing
- EEG and Brain-Computer Interfaces
- Control Systems and Identification
- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
- Digital Filter Design and Implementation
- Advancements in PLL and VCO Technologies
National University of Defense Technology
2022-2024
Abstract Digital differentiators enable the computation of derivative a continuous-time signal at discrete time instances, and they are used in many processing applications. This paper derives unified filter order estimate for digital that realized with linear-phase finite-length impulse response filters designed minimax sense. The is useful high-level system design when assessing implementation complexity it enables fewer designs finding minimal required to satisfy prescribed tolerable...
In this paper, two different timing-mismatch compensation strategies for two-channel time-interleaved analog-to-digital converters are comprehensively analyzed and compared. the first strategy (SA), one channel serves as a reference channel, other is compensated to match using timing mismatch between channels. second (SB), both channels each other, half value of with signs. For SB, paper introduces novel structure that utilizes parallel differentiator-multiplier (PDM) branches. Expressions...
This brief introduces a compensation structure for frequency response mismatch (FRM) errors in two-channel time-interleaved analog-to-digital converters (TI-ADCs) based on polynomial models of the channel responses. It can be used any Nyquist band and it comprises parallel error approximation branches (EABs), each branch consisting fixed differentiator unique degree cascaded with variable multiplier simple modulator. suffices to alter multipliers when channels change, thereby avoiding online...
With the ever-growing demands for sampling rate, conversion resolution, as well lower energy consumption, memristor-based neuromorphic analog-to-digital converters (MN-ADC) becomes one of most potential approaches to break bottleneck traditional ADCs. However, online trainable MN-ADCs are not designed be easily integrated into 1T1R crossbar array, meanwhile suffering from device non-idealities, which makes it difficult realize high-speed and accurate conversion. To overcome these issues,...