Purpose The study advances an enhanced model encompassing psychological involvement, denoted as the continuum (PCM) and perceived customer service quality intermediaries in association between subjective knowledge (SCK) behavioral loyalty. purpose of this is to assess mediating role engagement consumers' relationship SCK loyalty among members nonprofit sports organizations. Additionally, aims examine impact membership duration on consumer Design/methodology/approach used a quantitative...

The mass transfer enhanced cathode flow field with little pressure loss is a key factor to proton exchange membrane fuel cell (PEMFC) design. A new type of incorporating ship-shaped baffles which enhances while causes parasitic power proposed in this study. Effects length, breadth, molded depth, liquid level height and draft depth the ship-like baffle on water removal PEMFC performance are investigated numerically. Results show that could accelerate removal. Slim big surface helps break...

With the rapid development of online tourism, a significant number sustainable hotels have established cooperation with travel agencies (OTAs) for room sales. This study introduces an analytical framework supply chain model, involving hotel and OTA. Utilizing Stackelberg game theory, we investigate two parties’ decision-making processes as they consider contracts reselling, cost sharing, revenue sharing. Our analysis reveals that sharing are more effective in motivating to implement...

Actin microfilaments (F-actin) serve as the track for directional movement of organelles in plant cells. In actively growing cells, F-actin often form robust bundles that trespass cellular dimension. To test how network was employed peroxisome movement, we wished to disturb actin organization by genetically compromising function villin (VLN) proteins primary bundling factor Arabidopsis thaliana do so, isolated T-DNA insertional mutants three VLN genes were most expressed vegetative tissues....

Placement has always been the most time-consuming part of field programmable gate array (FPGA) compilation flow. Conventional simulated annealing unable to keep pace with ever increasing sizes designs and FPGA chip resources. Without utilizing information circuit topology, it relies on large amounts random swap operations, which are time-costly. This paper proposes an adaptive range-based algorithm improve behavior operations limit distances by introducing concept range-limiting strategy for...

As a highly automated carrying vehicle, an guided vehicle (AGV) has been widely applied in various industrial areas. The collision avoidance of AGV is always problem factories. Current solutions such as inertial and laser guiding have low flexibility high environmental requirements. An INS (inertial navigation system)-UWB (ultra-wide band) based system introduced to improve the safety electronic map factory established UWB anchor nodes are deployed order realize accurate positioning....

This paper presents low-power complementary pass-transistor adiabatic logic (CPAL) using two-phase power-clocks instead of four-phase ones. The CPAL uses for evaluation and transmission gates energy-recovery. It is more suitable design flip-flops sequential circuits, as it fewer transistors than conventional CMOS gate-based implementations other circuits such 2N-2N2P. Adiabatic (D, T JK) based on the are introduced. A practical system realized with proposed demonstrated. SPICE simulations...

The scaling of transistor sizes has resulted in dramatic increase leakage currents. sub-threshold and gate leakages have now become a major contributor to total power dissipations. This paper presents two flip-flops based on dual-threshold CMOS multiple reduction techniques reduce their In the DT-TG FF (Dual-Threshold Transmission Gate Flip-Flop), some transistors non-critical paths use high-threshold devices currents, while other critical low-threshold maintain performance. MLRT (Multiple...

This paper presents a low power channel-length biasing pulse flip-flop (CLBPFF) aimed at substantial reduction in leakage power. The proposed CLBPFF has been compared with the transmission gate (TGFF) and hybrid latch (HLFF) term of dissipation, delay energy product (EDP). Voltage scaling for also carried out. All flip-flops are simulated using 45nm CMOS technology by varying supply voltage from 1.1V to 0.6V 0.1V steps. Taken as an example, practical sequential system realized is...

A dual transmission gate adiabatic logic (DTGAL) suitable for driving large capacitance is presented. DTGAL, has no non-adiabatic energy loss on output loads by using feedback control from next-stage buffer outputs. The minimization of consumption was investigated choosing the optimal size DTGAL circuits. 64/spl times/64-b SRAM designed. proposed circuits are used to recover charge switching bit-lines, word-lines, and address decoders in fully manner. power significantly reduced as...

This paper presents an improved single-phase adiabatic circuit for CAL (Clocked Adiabatic Logic). In the circuits, auxiliary clock uses sinusoidal wave to recycle charge of lines, while conventional circuits adopts square wave. Pre-adiabatic flip-flops and sequential based on are proposed. With TSMC 0.18μm CMOS process, energy loss proposed is greatly reduced compared implementation.

A new low-power adiabatic logic, complementary pass-transistor logic (CPAL), is presented. The CPAL circuit uses for logic-evaluation and transmission gates energy-recovery, to realize efficient energy transfer low loss. non-adiabatic loss of output loads has been eliminated completely. An inverter chain was simulated verified using MOSIS 0.25mm CMOS technology. Simulation results with SPICE show that the 2.5 3 times more than 2N-2N2P 9 less dissipative static clock rates ranging from 25...

In present CMOS circuits, the power dissipation caused by leakage current cannot be neglected anymore. An effective way to reduce is dual-threshold techniques. Low-threshold transistors are assigned critical paths of circuits enhance performance, while high-threshold non-critical current. This paper proposes a new transmission gate flip-flop based on technique its power. Simulation results show that proposed saves 20-30% and 40-50% compared with single-threshold one gate-length biasing one,...

In this paper, the standard cells of high-speed low-power MCML circuits with near-threshold computing are developed. The basic include buffer/inverter, AND/NAND, XOR/XNOR, multiplexer, and full adder. layout, abstract design standard-cell characters described at a NCSU FreePDK 45nm technology. 2-bit multiplier is verified by using cells. For normal supply voltage, gates can save more energy have better performance than traditional CMOS counterparts 1GHz or higher operation frequencies....

This paper proposes the realization of dual-threshold independent-gate FinFETs by optimizing FinFET process parameters including electrode work function, silicon body thickness, and oxide thickness. The optimum values are derived using BSIM-IMG SPICE model for devices. In (IG) FinFETs, a high-threshold IG is logically equivalent to two short-gate (SG) in series, while low-threshold one SG parallel. complementary static logic circuits differential cascode voltage switch based on proposed...

MOS Current-Mode Logic (MCML) is usually used for high-speed applications. In this paper, the design method of low-power MCML addressed. The layout implementations basic gates are presented at a NCSU FreePDK 45nm technology. post-layout simulations carried out. For normal supply voltage, can save more energy and have better performance than traditional CMOS counterparts 1GHz or higher operation frequencies. Scaling down voltage circuits investigated. results show that power consumption be...

This paper presents the power optimization of complementary pass-transistor adiabatic logic (CPAL) and design sequential circuits. CPAL circuits have more efficient energy transfer recovery, because non-adiabatic loss output loads has been completely eliminated by using for evaluation transmission gates energy-recovery. The minimization consumption was investigated choosing optimal size transistors. Adiabatic flip-flops (D, T JK) are introduced. A practical system designed with proposed...

In view of changing the type energy conversion in CMOS circuits, this paper investigates low-power characteristics complementary pass-transistor logic (CPL) circuits using AC power supply. On basis, adiabatic CPL two-phase power-clocks are described, which consist pure NMOS transistors. Adiabatic flip-flops with reset terminals also introduced. A practical sequential system is demonstrated. The suitable for design and as it uses fewer transistors than other similar implementations.

This paper presents adiabatic flip-flops with data-retention function, which are realized the CPAL (complementary pass-transistor logic) circuits using two-phase power-clocks. In proposed flip-flops, active enable and refresh terminals added for power-gating operation. A practical sequential system a mode-5times5times5 counter is demonstrated scheme. Because of scheme, use fewer transistor count compared four-phase ones. SPICE simulations show that energy loss can be greatly reduced by...

With rapid technology scaling, the proportion of static power catches up with dynamic gradually. To decrease leakage is becoming more and important in low-power design. Base on pact that PMOS transistors have an order magnitude smaller gate than NMOS ones, p-type complementary pass-transistor logic (P-CPL) differential cascade voltage switch (P-DCVSL) are proposed to reduce this paper. For example, two full adders based P-CPL P-DCVSL circuits verified. All simulated using 130 nm, 65 nm 32...