A5050556210- Semiconductor materials and devices
- Ferroelectric and Negative Capacitance Devices
- Low-power high-performance VLSI design
- Advanced Memory and Neural Computing
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Data Storage Technologies
- Ferroelectric and Piezoelectric Materials
- Parallel Computing and Optimization Techniques
- MXene and MAX Phase Materials
- VLSI and Analog Circuit Testing
- Advancements in PLL and VCO Technologies
- Analog and Mixed-Signal Circuit Design
- Magnetic properties of thin films
- VLSI and FPGA Design Techniques
- Photonic and Optical Devices
- Acoustic Wave Resonator Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Machine Learning and ELM
- Radio Frequency Integrated Circuit Design
- Copper Interconnects and Reliability
- Cellular Automata and Applications
- Phase-change materials and chalcogenides
- Multiferroics and related materials
- Nanowire Synthesis and Applications
- Microwave Engineering and Waveguides
Toshiba (Japan)
2004-2018
Toshiba (South Korea)
1996-2005
An 87.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent architecture, three new scaling techniques - octal parasitic sensing scheme, and dual metal plateline scheme reduce from 100 fF 60 fF. As a result, cell signal of ±220 mV achieved even the size 0.252 ¿m . 800 Mb/s/pin read/write bandwidth at 400 MHz...
A new chain ferroelectric random access memory-a FRAM-has been proposed. memory cell consists of parallel connection one transistor and capacitor, block plural cells connected in series a selecting transistor. This configuration realizes the smallest 4 F/sup 2/ size using planar so far reported, access. The chip proposed FRAM can be reduced to 63% that conventional when 16 are series. fast nondriven half-V/sub dd/ cell-plate scheme, as well driven applicable without polarization switching...
In this paper, the overview of FeRAMs, key techniques and technical trends for scaled marketing strategy are presented. Advantages FeRAM compared with other emerging memories, 1T1C-FeRAM chain FeRAM, trend memory cells chip features, various device circuit to achieve low voltage FeRAMs such as capacitor damage suppression cell signal enhancement demonstrated. High-speed embedded solution, future direction, take full advantage merits also discussed.
This paper describes a novel circuit technology with Surrounding Gate Transistors (SGT's) For ultra high density DRAM's. In order to reduce the chip size drastically, an SGT is employed all transistors within chip. SGT's connected in series and common source have been newly developed for core circuit, such as sense amplifier designed by tight design rule. Furthermore, inherent cell array noise caused relaxed open bit line (BL) architecture, killer placed word (WL) shunt region twisted BL...
An open/folded bit-line (BL) arrangement for scaled DRAM's is proposed. This BL offers small die size and good array noise immunity. In this arrangement, one of an open pair placed in between a folded pair, the sense amplifiers (SA's) BL's those are alternately memory arrays. features 6F/sup 2/ cell, where F device feature size, relaxed SA pitch 6F. The 64-Mb DRAM can be reduced to 81.6% compared with using conventional arrangement. BL-BL coupling one-half that thanks shield effect. Two new...
An application that takes advantage of FeRAM characteristics is replacing current DRAM, which then becomes high-performance nonvolatile RAM cache. This improves system performance for many kinds computer systems, including mobile PCs, cellular phones, digital video products, and storage systems such as SSDs. However, the highest capacity in RAMs allow frequent cache reads writes limited to 64 Mb. The maximum read bandwidth 400 Mb/s write 200 memories reported date. FeRAm was demonstrated 4M...
This paper proposes a new ladder FeRAM ar chitecture with capacitance-coupled-bitline (CCB) cells for high-end embedded applications. The architecture short-circuits both electrodes of each ferroelectric capacitor at every standby cycle. overcomes the fatal disturbance problem inherent to CCB cell, and halves read/write cycle time by sharing plateline its driver 32 in two neighboring blocks. configuration realizes small 0.35 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This paper demonstrates the first 8-Mb chain ferroelectric RAM (chain FeRAM) with 0,25-/spl mu/m 2-metal CMOS technology. A small die of 76 mm/sup 2/ and a high average cell/chip area efficiency 57.4 % have been realized by introducing not only architecture but also four new techniques: 1) one-pitch shift cell realizes size 5.2 /spl mu/m/sup 2/; 2) hierarchical wordline reduces row-decoder plate-driver areas without an extra metal layer; 3) small-area dummy scheme capacitor to 1/3...
A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with an effective cell-size of 0.7191mum while eliminating BL-BL coupling noise. high-speed ECC circuit cell data write-back scheme achieves read/write cycle time 60ns 200MB/S burst
A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. newly developed quad bitline architecture, which combines folded configuration with shield scheme, eliminates bitline-bitline (BL-BL) coupling noise. The architecture also reduces the number of sense amplifiers and activated bitlines, resulting in reduction die size by 6.5% cell array power consumption 28%. Fast read/write 60-ns cycle time as well reliability improvement are realized two...
This paper demonstrates the hard disk drive (HDD) performance improvement by nonvolatile FeRAM cache. First, an array architecture and data path design of 128 Mb chain to meet HDD specifications, a total power supply system for application are presented. A 1.6 GB/s read/write bandwidth with page length 512 Byte sector size, protection against sudden failure have been realized. Second, concept cache utilize memory maximum ignoring flush commands issued from Windows OS is Third, simulated...
New gate logics, standby/active mode logic I and II, for future 1 Gb/4 Gb DRAMs battery operated memories are proposed. The circuits realize sub-l-V supply voltage operation with a small 1-/spl mu/A standby subthreshold leakage current, by allowing mA in the active cycle. Logic is composed of gates using dual threshold (Vt) transistors, it can achieve low adopting high Vt transistors only to which cause current. II uses lines, reduces controlling dissipating delay reduced 30-37% at 1.5-1.0...
A ferroelectric capacitor overdrive with shield-bitline drive for 1.3 V chain FeRAM has been verified using a 0.13 ¿m 576 Kb test chip 0.719 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell. This technique applies 0.24 bias to capacitors without increasing stress and bitline capacitance. The measured tail-to-tail cell signal is improved by 100 mV doubled in array operation.
A 64-Mb CMOS dynamic RAM (DRAM) measuring 176.4 mm/sup 2/ has been fabricated using a 0.4- mu m N-substrate triple-well CMOS, double-poly, double-polycide, double-metal process technology. The asymmetrical stacked-trench capacitor (AST) cells, 0.9 m*1.7 each, are laid out in PMOS centered interdigitated twisted bit-line (PCITBL) scheme that achieves both low noise and high packing density. Three circuit techniques were developed to meet high-speed requirements. Using the preboosted word-line...
A 7-transistor static random access memory (SRAM), in which cell data are written by capacitive coupling, is proposed. In the 7T-SRAM configuration, traditional read/write port using two pass-gates (PGs), used 6T-SRAM, eliminated and read transistors such as 8T-SRAM equalizer for node pair installed. This transistor also acts a coupling capacitor writing external after floating paired nodes. The elimination of current-drive via PGs operation solves current-conflict problems. No degradation...
This 3.3V 64Mb DRAM in a 176.4mm² die has 33ns typical RAS access time and 15ns column address time. The key to small high reliability is an asymmetrical stacked trench capacitor (AST) cell pMOS centered inter-digitated twisted bit line (PCITBL) scheme. Three circuit techniques are developed meet speed requirements: pre boosted wordline-driveline, bypassed sense-amplifier drive 3-stage differential amplifier with directly-driven data-out buffer.
An experimental 256-Mb dynamic random access memory using a NAND-structured cell (NAND DRAM) has been fabricated. The four cells connected in series, which reduces the area of isolation between adjacent and also bit-line contact area. per bit measures 0.962 mu m/sup 2/, 0.4- m CMOS technology, is 63% comparison with conventional cell. In order to reduce die size, time division multiplex sense-amplifier (TMS) architecture, sense amplifier shared by lines, newly introduced. chip 464 mm/sup 68%...
We have successfully developed a 0.602 /spl mu/m/sup 2/ nestled 'Chain' FeRAM cell technology for 64Mbit FeRAM. In the pair of capacitors on same node can be close to each other A combination one mask etching process ferro-electric and structure drastically scaled down size 2/. The was reduced 32% previous work. Signal window 600 mV obtained by after full integration three-metal CMOS technology.
This paper demonstrates the 32-Mb chain ferroelectric RAM (chain FeRAM) with 0.2-μm three-metal CMOS technology. A small die size of 96 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a high cell/chip area efficiency 65.6% are realized not only by cell using capacitor-on-plug technology but also two key techniques that utilize process: 1) compact memory block structure eliminates plateline reduces selector 2) segment/stitch array...
This paper presents highly reliable reference bitline bias designs for 64 Mb and 128 chain FeRAM™. The hysteresis shape deformation of ferroelectric capacitor due to temperature variation causes cell signal level shifts both "1" "0" data. chip is designed keep intermediate value data at any operating temperatures from -40 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C 85 by introducing a modified band-gap circuit with 3 bit...
A nonvolatile chain FRAM adopting a new cell-plate-line drive technique was demonstrated. Two key circuit techniques, two-way metal cell-plate line and shared with 16 cells, reduce delay to 7 ns plate area 1/5. The total delay, including cell transistor due eight cells in series, is reduced 15 /spl mu/s, contrast 30-100-ns of the conventional FRAM. die size 86% that by reduction driver sense amplifier area, assuming same memory size. prototype 16-kb chip fabricated using 0.5 mu/m rule...
An excellent 64Mb chain FeRAMtrade using a highly reliable capacitor with damage-robust MOCVD-PZT and SrRuO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /IrO xmlns:xlink="http://www.w3.org/1999/xlink">2 </sub> top electrode (TE) is successfully demonstrated for the first time. A very large signal margin of 540mV at 1.8V achieved as small 0.19μm <sup xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Large sensing well maintained...
An embedded DRAM using a standard NAND flash memory process has been demonstrated for the first time. This without extra costly manufacturing realizes 2.4 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{2}$</tex> </formula> /Mb macro density and provides large-capacity on-chip page buffers data caches memories to enhance their performances. A 32 KB buffer with 1.5...
This paper presents fast 10-ns read/write cycle FeRAM with small 0.35μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell using highly reliable large ferroelectric capacitor of 0.145μm and compatible process logic-LSI.