During the last decade, extensive research has been carried out on subject of low-cost sensor platforms for air quality monitoring. A key aspect when deploying such systems is measured data. Calibration especially important to improve data monitoring devices. The must comply with regulations issued by national or international authorities in order be used regulatory purposes. This work discusses challenges and methods suitable calibrating a platform developed our group, Airify, that unit...

This paper introduces a new approach to cost-effective, high-throughput hardware designs for low-density parity-check (LDPC) decoders. The proposed approach, called nonsurjective finite alphabet iterative decoders (NS-FAIDs), exploits the robustness of message-passing LDPC inaccuracies in calculation exchanged messages, and it is shown provide unified framework several previously literature. NS-FAIDs are optimized by density evolution regular irregular codes, different tradeoffs between...

This paper proposes a FPGA implementation based on sliding processing window for Harris corner algorithm. It represents one of the most frequently used pre-processing method, wide variety image algorithms, such as feature detection, motion tracking, registration, etc.. relies series sequential steps, each an outputted by previous step. The purpose is to avoid storing intermediate results stages in external memory or utilize large line buffers typically implemented with BRAM blocks....

This paper first proposes two new LDPC decoding algorithms that may be seen as imprecise versions of the Offset Min-Sum (OMS) decoding: Partially OMS, which performs only partially offset correction, and Imprecise introduces a further level impreciseness in check-node processing unit. We show they allow significant reduction memory (25% with respect to baseline) interconnect, we propose cost-efficient unit architecture, yielding cost 56% baseline. implement FPGA-based layered decoder...

This brief presents a dedicated unit for the combined operation of floating-point (FP) division followed by addition/subtraction-the divide-add fused (DAF). The goal this is to increase performance and accuracy applications where frequent, such as interval Newton's method or polynomial approximation. proposed DAF similar architecture FP multiply-accumulate units. main difference represented divider, which implemented using digit-recurrence algorithms. An important design tradeoff regarding...

This paper proposes a holistic approach that addresses both the message mapping in memory banks and pipeline-related data hazards low-density parity-check (LDPC) decoders. We consider layered hardware architecture using single read/single write port banks. The throughput of such an is limited by access conflicts, due to improper banks, pipeline hazards, delayed update effect. solve these issues by: 1) residue-based scheduling reduces related 2) off-line algorithms for optimizing read...

This paper introduces a new theoretical framework, akin to the use of imprecise message storage in Low Density Parity Check (LDPC) decoders, which is seen as an enabler for cost-effective hardware designs. The proposed framework one Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), and it shown provide unified approach several designs previously literature. NS-FAIDs are optimized by density evolution WiMAX irregular LDPC codes we show they different trade-offs between complexity...

Implementation of Quasi-Cyclic (QC) Low Density Parity-Check (LDPC) decoder on FPGA devices has shown great interest in both wireless communication, as well error correction for Flash memories. This paper presents an flooded LDPC which uses multiple codeword processing efficient memory utilization. It is based a partially parallel implementation, relies blocks message passing between the units. We obtain utilization by packing messages corresponding to codewords into same Block RAM word. The...

Probabilistic gradient descent bit-flipping (PGDBF) is a hard-decision decoder for low-density parity-check (LDPC) codes, which offers significant improvement in error correction, approaching the performance of soft-information decoders on binary symmetric channel. However, this outstanding known to come with an augmentation complexity, compared non-probabilistic bit flipping (GDBF), becoming drawback decoder. This paper presents new approach implementing PGDBF decoding quasi-cyclic LDPC...

This paper proposes a layered decoder architecture for array QC-LDPC codes which targets tens of Gbps data rates. It relies on layer unrolling with pipeline stages in between layers, allowing simultaneous decoding multiple layers. The most important features the proposed are: (i) fully parallel processing units within each (ii) hardwired interconnect that allows removal high cost variable shift units, (iii) A posteriori log-likelihood ratio (AP-LLR) message memory type storage is replaced by...

This paper proposes an FPGA based flooded architecture for quasi-cyclic (QC) LDPC decoder. The message computation both check and variable node update is done using a parallel scheme of number processing units equal to the expansion factor QC matrix. proposed performs serial messages by dedicated units. way, reduced memory word size used, which lead reduction BRAM blocks. Multiple frame decoding used in order increase throughput usage. Implementation results WiMAX (1152, 2304) irregular code...

This paper presents gate level delay dependent probabilistic fault models for CMOS circuits operating at sub-threshold and near-threshold supply voltages. A bottom-up approach has been employed: SPICE simulations have used to derive higher error implemented using Verilog HDL. HSPICE Monte-Carlo show that the nature of these faults is due process-voltage-temperature (PVT) variations which affect very low For analysis, mutant based simulated injection (SFI) techniques employed combinational...

Floating-point (FP) multiply-add fused (F1*F2 ± F3) and multiply-accumulate represent the most common arithmetic operation in a wide range of applications, such as graphic processing, multimedia or FP digital signal processing (DSP). This study proposes units for low-precision formats (IEEE 16-bit half precision 32-bit single precision) which rely on modern Field Programmable Gate Array (FPGA) features available integer multiply-accumulate-based support built-in FPGA DSP blocks. These are...

This paper proposes an FPGA based layered architecture for quasi-cyclic (QC) irregular LDPC decoder. Our approach is on merging variable and check node processing into one single variable-check (VCN) unit. Layer message computation done using a parallel scheme of number VCNs equal to the expansion factor QC matrix. The proposed characterized by serial posteriori LLRs specific high frequency VCN unit implementation ROM memories. In our data conversions as well additions comparators are...

This paper addresses the problem of evaluating Fault Tolerance Algorithms and Methodologies (FTAMs) designed for quantum systems, by adopting Simulated Injection methodology from classical computation. Due to their wide spectrum applications (including circuit simulation) hierarchical features, HDLs were employed performing fault injection, as prescribed guidelines QUERIST project. At same time, injection techniques taken simulation had be adapted computation requirements, including specific...

This paper proposes a new approach for the optimization process of interval addition and multiplication floating point units. For addition/subtraction, an adder exploiting parallelism double path structure is used. The two additions needed are performed simultaneously on different data paths. Therefore, performance proposed can be same as that individual adders, but with much reduced cost overhead. Regarding multiplication, multiplier architecture was designed, in order to suitable pipelined...

This paper proposes memory efficient FPGA implementations for layered quasi-cyclic (QC) LDPC decoders, based on the Self-Correcting Min-Sum (SCMS) algorithm. We address problem of high overhead required by SCMS decoders compared to conventional (MS), proposing two improvements. These require changes in flow/rule algorithm, order avoid storing signs and erasure bits variable node messages. Three with serial a-posteriori log likelihood ratios (AP-LLR) processing have been implemented: (1)...

This paper proposes an accelerator for Canny edge detection implemented on FPGA. The proposed architecture relies a moving window consisting of 7×8 pixels, which performs the more computational complex operations algorithm: smoothing, gradient's magnitude and direction computation, non-maximum suppression double thresholding. By employing window, intermediate results are stored within FPGA, without need to buffer them in large memory structures. Furthermore, design has high throughput rate,...

In this letter, we address the issue of early stopping criterion for layered LDPC decoders, aiming at more safeness with low hardware cost and minimum latency. We introduce a new on-the-fly measure in decoder, called in-between layers partial syndrome, define family criteria, different tradeoffs among complexity, latency, performance. Numerical results show that our criteria surpass existing solutions, can be as safe full-syndrome detection, down to frame error rates (FERs) FER = 10 <sup...

This paper presents a cost effective FPGA fault emulation technique for probabilistic errors. The problem it addresses is how to efficiently inject faults in many locations within circuit under test. For this purpose, the emulated injection (EFI) components proposed are trade-off between desire speed/performance and inherent physical device limitations of FPGA. method also allows exploring best option with minimal effort. solution enough flexibility be able deal different EFI architectures...

In this paper we perform a fault tolerance assessment of flooded Low Density Parity Code (LDPC) decoders affected by probabilistic timing errors, characteristic to sub-powered CMOS circuits. We investigate the error correction capability - in terms Frame Error Rate (FER) faulty Min-Sum (MS) and Self-Corrected (SCMS) LDPC architectures for both Binary Input Additive White Gaussian Noise (BIAWGN) Symmetric Channel (BSC) channel models FAID BSC model. The analysis is performed using multi-level...

A novel check node unit architecture for low‐density parity (LDPC) decoders, which avoids the usage of carry‐based comparators computation required first and second minimum values, is presented. It relies on a one‐hot representation input messages’ magnitude, obtained by q ‐to‐2 decoders. The two minimums are computed using an OR tree modified leading zero counter. proposed imprecise, as not correctly when it equal to one. implementation results analysis error correction capability show that...

This paper proposes data-dependent reliability evaluation methodology for digital systems described at Register Transfer Level (RTL). It uses a hybrid hierarchical approach, combining ...