Yuhao Wang

ORCID: 0000-0002-9724-9667
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About
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Research Areas
  • Advanced Memory and Neural Computing
  • Ferroelectric and Negative Capacitance Devices
  • Semiconductor materials and devices
  • Quantum and electron transport phenomena
  • Quantum-Dot Cellular Automata
  • Machine Learning and ELM
  • Phase-change materials and chalcogenides
  • Topological Materials and Phenomena
  • Semiconductor materials and interfaces
  • Advancements in Semiconductor Devices and Circuit Design
  • Neural Networks and Reservoir Computing
  • Magnetic properties of thin films
  • Advanced Thermoelectric Materials and Devices
  • Stochastic Gradient Optimization Techniques
  • Blind Source Separation Techniques
  • Sparse and Compressive Sensing Techniques
  • Cryptographic Implementations and Security
  • Analog and Mixed-Signal Circuit Design
  • Neural dynamics and brain function
  • Scientific Computing and Data Management
  • Advanced Thermodynamics and Statistical Mechanics
  • Liquid Crystal Research Advancements
  • Graph Theory and Algorithms
  • Polydiacetylene-based materials and applications
  • Biomedical Text Mining and Ontologies

L'Alliance Boviteq
2025

Tsinghua University
2025

Xi'an Jiaotong University
2024

University of Nottingham
2023

Chinese Academy of Sciences
2022

University of Chinese Academy of Sciences
2022

Institute of Microelectronics
2022

Alibaba Group (China)
2020-2021

Synopsys (United States)
2016-2017

Nanyang Technological University
2012-2016

The data-oriented applications have introduced increased demands on memory capacity and bandwidth, which raises the need to rethink architecture of current computing platforms. logic-in-memory is highly promising as future logic-memory integration paradigm for high throughput data-driven applications. From technology aspect, one recently nonvolatile device, domain-wall nanowire (or race-track) not only shows potential power efficient memory, but also by its unique physics spintronics. This...

10.1109/tnano.2015.2447531 article EN IEEE Transactions on Nanotechnology 2015-06-19

Big-data storage poses significant challenges to anonymization of sensitive information against data sniffing. Not only will the encryption bandwidth be limited by I/O traffic, transfer between processor and memory also expose input-output mapping intermediate computations on channels that are susceptible semi-invasive non-invasive attacks. Limited simplistic cell-level logic, existing logic-in-memory computing architectures incapable performing complete process within at reasonable...

10.1109/tifs.2016.2576903 article EN IEEE Transactions on Information Forensics and Security 2016-06-07

Graphene aerogels hold huge promise for the development of high-performance pressure sensors future human-machine interfaces due to their ordered microstructure and conductive network. However, application is hindered by limited strain sensing range caused intrinsic stiffness porous microstructure. Herein, an anisotropic cross-linked chitosan reduced graphene oxide (CCS-rGO) aerogel metamaterial realized reconfiguring from a honeycomb buckling structure at dedicated cross-section plane. The...

10.1021/acs.nanolett.4c03706 article EN cc-by Nano Letters 2024-09-11

Emerging resistive random-access memory (RRAM) can provide non-volatile storage but also intrinsic logic for matrix-vector multiplication, which is ideal low-power and high-throughput data analytics accelerator performed in memory. However, the existing RRAM-based computing device mainly assumed on a multi-level analog computing, whose result sensitive to process non-uniformity as well additional AD- conversion I/O overhead. This paper explores binary RRAM-crossbar. Accordingly, one...

10.1109/aspdac.2016.7428024 article EN 2016-01-01

Material challenges are the key issue in Majorana research, where surface disorder constrains device performance. Here, we tackle this challenge by embedding PbTe nanowires within a lattice-constant-matched crystal. The wire edges shaped self-organized growth instead of lithography, resulting nearly atomically flat facets along both cross-sectional and longitudinal directions. Quantized conductance is observed at zero magnetic field with channel lengths maximally reaching 1.7 μm,...

10.1021/acs.nanolett.4c05708 article EN Nano Letters 2025-01-07

We investigate the anisotropic behaviors in PbTe and PbTe-Pb hybrid nanowires. In previous studies on PbTe, wire-to-wire variations anisotropy indicate poor device control, posing a serious challenge for applications. Here, we achieve reproducible nanowires through substantial reduction of disorder. then couple to superconductor Pb, observe pronounced deviation behavior compared bare This is gate-tunable attributed spin-orbit interaction orbital effect, controlled by charge transfer between...

10.48550/arxiv.2501.04345 preprint EN arXiv (Cornell University) 2025-01-08

In this paper, we present the work executed on re-architecting BioHackrXiv during international ELIXIR BioHackathon Europe 2023 in Barcelona, Spain. is a scholarly publication service for biohackathons and codefests that target biology biomedical sciences spirit of pre-publishing platforms.

10.37044/osf.io/c8jw6_v1 preprint EN 2025-04-02

The phase transition behaviors of sodium-layered oxide (SLO) cathodes play an important role in their electrochemical performances at high voltages. Specifically, SLOs experience a from the P to OP intergrowth with Na-deficient O layers, leading sluggish Na extraction/insertion kinetics, severe strain formation, and reactive activity electrolytes. In addition normally used engineering strategies such as bulk doping, we demonstrate here that Mn-gradient surface layer can significantly tune O3...

10.1021/acsnano.5c01904 article EN ACS Nano 2025-04-21

Image processing in conventional logic-memory I/O-integrated systems will incur significant communication congestion at memory I/Os for excessive big image data exa-scale. This paper explores an in-memory machine learning on neural network architecture by utilizing the newly introduced domain-wall nanowire, called DW-NN. We show that all operations involved can be mapped to a logic-in-memory non-volatile nanowire. Domain-wall nanowire based logic is customized within storage. As such, both...

10.1109/aspdac.2014.6742888 article EN 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) 2014-01-01

Compressive sensing is widely used in biomedical applications, and the sampling matrix plays a critical role on both quality power consumption of signal acquisition. It projects high-dimensional vector data into low-dimensional subspace by matrix-vector multiplication. An optimal can ensure accurate reconstruction and/or high compression ratio. Most existing optimization methods only produce real-valued embedding matrices that result large energy during In this paper, we propose an efficient...

10.1109/tbcas.2016.2597310 article EN IEEE Transactions on Biomedical Circuits and Systems 2016-11-16

The widely applied Advanced Encryption Standard (AES) encryption algorithm is critical in secure big-data storage. Data oriented applications have imposed high throughput and low power, i.e., energy efficiency (J/bit), requirements when applying AES encryption. This paper explores an in-memory using the newly introduced domain-wall nanowire. We show that all operations can be fully mapped to a logic-in-memory architecture by non-volatile nanowire, called DW-AES. experimental results DW-AES...

10.5555/2616606.2616831 article EN Design, Automation, and Test in Europe 2014-03-24

As one recently introduced non-volatile memory (NVM) device, domain-wall nanowire (or race-track) has shown potential for main storage but also computing capability. In this paper, the is studied a memory-based platform towards ultra-low-power big-data processing. One based logic-in-memory architecture proposed processing, where deployed as data well XOR-logic comparison and addition operations. The circuits are evaluated by SPICE-level verifications. Further applications of general-purpose...

10.1109/islped.2013.6629318 article EN 2013-09-01

As one recently introduced non-volatile memory (NVM) device, domain-wall nanowire (or race-track) has shown potential for main storage but also computing capability. In this paper, the is studied a memory-based platform towards ultra-low-power big-data processing. One based logic-in-memory architecture proposed processing, where deployed as data well XOR-logic comparison and addition operations. The circuits are evaluated by SPICE-level verifications. Further applications of general-purpose...

10.5555/2648668.2648748 article EN International Symposium on Low Power Electronics and Design 2013-09-04

The widely applied Advanced Encryption Standard (AES) encryption algorithm is critical in secure big-data storage. Data oriented applications have imposed high throughput and low power, i.e., energy efficiency (J/bit), requirements when applying AES encryption. This paper explores an in-memory using the newly introduced domain-wall nanowire. We show that all operations can be fully mapped to a logic-in-memory architecture by non-volatile nanowire, called DW-AES. experimental results DW-AES...

10.7873/date.2014.196 article EN Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 2014-01-01

As one of the newly introduced resistive random access memory (ReRAM) devices, this paper has shown an in-depth study conductive-bridging (CBRAM) for non-volatile (NVM) computing. Firstly, a CBRAM-crossbar based is evaluated with accurate physical-level model and circuit-level characterization. It then deployed as NVM component 3D hybrid integration SRAM/DRAM, where layer designed data-retention under power gating to reduce leakage from SRAM/DRAM at other layers. Moreover, block-level scheme...

10.1145/2333660.2333709 article EN 2012-07-30

The spiking neural network (SNN), closely inspired by the human brain, is one of most powerful platforms to enable highly efficient, low cost, and robust neuromorphic computations in hardware using traditional or emerging electron devices within an integrated system. In implementation, building artificial neurons fundamental for constructing whole However, with slowing down Moore's Law, complementary metal-oxide-semiconductor (CMOS) technology gradually fading unable meet growing needs...

10.1016/j.jnlest.2022.100177 article EN cc-by-nc-nd Journal of Electronic Science and Technology 2022-11-17

Non-volatile memory (NVM) is one recent promising solution to build the next generation of system. Compared other non-volatile devices such as flash, phase-change random-access-memory (PCRAM), memristor and etc., emerging conductive-bridge (CBRAM) has shown advantages in accessing speed, power endurance. In this paper, design 3D-stacked NVM explored with use CBRAM-crossbar. Specifically, accurate performance modeling CBRAM-crossbar structure studied within corresponding platform developed at...

10.1109/3dic.2012.6263047 article EN 2012-01-01

Topological insulator (TI) is recently discovered nano-device whose bulk acts as but surface behaves metal. As state information in a TI device conducted by ordered spins, it draws tremendous interest for ultra-low power computing. This paper shows state-space modeling and design exploration of non-volatile memory (NVM) design. The non-traditional electrical extracted modeled SPICE-like simulator. model the employed hybrid CMOS-TI NVM explorations both cell array. experiment results show...

10.1145/2765491.2765498 article EN 2012-07-04

As one recently introduced non-volatile memory (NVM) device, domain-wall nanowire (or race-track) shows not only potential as future memory, but also computing capacity in big-data processing under unique manipulation ability. In this paper, device is studied for a NVM-based platform, where all three parts: general purpose logic LUT, special of XOR and data storage are implemented by devices. application, matrix multiplication, which widely deployed applications such machine learning or web...

10.1109/nvmts.2013.6851053 article EN 2013-08-01

Exa-scale computing needs to re-examine the existing hardware platform that can support intensive data-oriented computing. Since main bottleneck is from memory, we aim develop an energy-efficie

10.2200/s00736ed1v01y201609eet008 article EN Synthesis lectures on emerging engineering technologies 2016-12-01

The widely applied Advanced Encryption Standard (AES) encryption algorithm is critical in secure big-data storage. Data oriented applications have imposed high throughput and low power, i.e., energy efficiency (J/bit), requirements when applying AES encryption. This paper explores an in-memory using the newly introduced domain-wall nanowire. We show that all operations can be fully mapped to a logic-in-memory architecture by non-volatile nanowire, called DW-AES. experimental results DW-AES...

10.7873/date2014.196 article EN Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 2014-01-01

Data analytics such as face recognition involves large volume of image data, and hence leads to grand challenge on mobile platform design with strict power requirement. Emerging non-volatile STT-MRAM has the minimum leakage comparable speed SRAM, is considered a promising candidate for data-oriented computing. However, there exists significantly higher write-energy when compared SRAM. Based use STT-MRAM, this paper introduces an energy-efficient in-memory accelerator sparse-representation...

10.7873/date.2015.0582 article EN Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 2015-01-01

Spin-transfer torque random access memory (STT-RAM) is one promising candidate for future non-volatile based computing, because of its fast time, high integration density and non-volatility. One major challenge STT-RAM to design robust readout circuit in the presence large MTJ resistance variations. The lack SPICE-like platform hinders validation hybrid STT-MTJ CMOS structure circuits. In this paper, we have introduced recently developed NVM-SPICE with array also non-destructive...

10.1109/nvmts.2013.6632865 article EN 2012-10-01
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