A5037892436- Advancements in PLL and VCO Technologies
- Analog and Mixed-Signal Circuit Design
- Radio Frequency Integrated Circuit Design
- VLSI and Analog Circuit Testing
- Interconnection Networks and Systems
- Semiconductor Lasers and Optical Devices
- Photonic and Optical Devices
- Low-power high-performance VLSI design
- Electrostatic Discharge in Electronics
- Integrated Circuits and Semiconductor Failure Analysis
- stochastic dynamics and bifurcation
- Optical Network Technologies
- Electromagnetic Compatibility and Noise Suppression
- Neural Networks and Applications
- Electronic Packaging and Soldering Technologies
Kobe University
2020
Panasonic (Japan)
2007-2020
Semiconductor Energy Laboratory (Japan)
2006
A process-independent adaptive bandwidth spread-spectrum clock generator (SSCG) with digitally controlled self-calibration techniques is proposed. By adaptively calibrating the VCO gain (K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</sub> ) and charge-pump (CP) current over C (I xmlns:xlink="http://www.w3.org/1999/xlink">CP</sub> /C), SSCG can realize not only but also process independence at each operating frequency. The innovative point...
We propose a method of reducing substrate noise and random fluctuations utilizing self-adjusted forward body bias (SA-FBB) circuit. To achieve this, we designed test chip that contained an on-chip oscilloscope for detecting dynamic from various frequency sources, another 10-M transistors measuring fluctuation tendencies. Under SA-FBB conditions, it reduced by 69.8% /spl sigma/(I/sub ds/) 57.9%.
We propose a multimodal PAM4/nonreturn to zero (NRZ) transceiver, including an adaptive ultra-wide range receiver and power noise-stabilized transmitter. The transmitter features PAM4 emphasis driver stabilizer, which are applied reduce distortion impact power-induced jitter. Installing aggressor circuit allowed us analyze the influence on input buffer of interface block whole system by varying frequency activation rate. multi-modal wide-range phase detector optimize jitter tolerance at each...
We propose a method of reducing quantization noise and spectrum peak utilizing an adaptive spread clocking PLL (SSC-PLL) circuit for Bi-directional AC coupled interface. To realize high speed, wide range, bi-directional long cable transceiver, we designed test chip that contained Equalizer, CDR, differential transceiver cable, also SSC-PLL with jitter optimization by bandwidth setting. Utilize this interface, it can be realized up to 810Mbps 20-m system ESD protection, reduction about -23dB...
A novel transceiver with adaptive power control (APC) using a process and frequency monitor (PFM) based on new optimization concept is proposed. The PFM employs gain calibration replica VCO operates in the background. test chip, employing amplitude scaling (AAS), bias (ABS), supply-voltage (AVS), achieved over wide frequency-range (0.05-3.4Gbps). At 100Mbps measured APC was reduced by 75% compared to conventional architecture without APC.
A multimodal PAM4/NRZ transceiver, including adaptive ultra-wide range receiver and power noise stabilized transmitter, is proposed. The features wide-range phase detector to optimize jitter tolerance for each speed while supporting both clock-forward clock-embedded mode. An CDR controller selects the optimum mode according transmitter performance reduce consumption ensuring interoperability. PAM4 emphasis driver stabilizer, which are applied reducing distortion impact induced jitter. test...
A transceiver with adaptive power control using a process and frequency monitor (PFM) is proposed. The PFM employs gain calibration replica voltage-controlled oscillator (VCO) operates in the background. five-bit digital code detected by VCO applied to an adaptive-amplitude driver, adaptive-bandwidth receiver, phase-locked loop. test chip was fabricated 110-nm CMOS achieved over wide range (0.05 3.4 Gb/s). At data rate of 100 Mb/s, measured consumption attained 75% lower than that...
With increasing technology scaling and the use of lower voltages, more research interest is being shown in variability-tolerant analog front end design. In this paper, we describe an adaptive amplitude control transmitter that operated using differential signaling to reduce temperature variability effect. It enables low power, voltage operation by synergy between Vth variation control. suitable for high-speed interface applications, particularly cable interfaces. By installing aggressor...