A5027316186- Parallel Computing and Optimization Techniques
- Interconnection Networks and Systems
- Advanced Data Storage Technologies
- Distributed and Parallel Computing Systems
- Cloud Computing and Resource Management
- Low-power high-performance VLSI design
- Embedded Systems Design Techniques
- Organ Transplantation Techniques and Outcomes
- Renal and Vascular Pathologies
- Advanced Memory and Neural Computing
- Organ Donation and Transplantation
- Renal Transplantation Outcomes and Treatments
- Urinary Tract Infections Management
- Radiation Effects in Electronics
- Advanced Image Processing Techniques
- Generative Adversarial Networks and Image Synthesis
- Distributed systems and fault tolerance
- Urological Disorders and Treatments
- Security and Verification in Computing
- Pelvic floor disorders treatments
- Digital Media Forensic Detection
- Kidney Stones and Urolithiasis Treatments
- Caching and Content Delivery
- CCD and CMOS Imaging Sensors
- Real-Time Systems Scheduling
New York University
2011-2023
Courant Institute of Mathematical Sciences
2019-2023
Mansoura University
2021-2022
Armed Forces Hospital
2022
National Authority for Remote Sensing and Space Sciences
2022
Ministry of Health
2022
City University of New York
2007-2020
New York City College of Technology
2020
Cairo University
1976-2017
Kuwait University
2014
We present a supercomputer-driven pipeline for in silico drug discovery using enhanced sampling molecular dynamics (MD) and ensemble docking. Ensemble docking makes use of MD results by compound databases into representative protein binding-site conformations, thus taking account the dynamic properties binding sites. also describe preliminary obtained 24 systems involving eight proteins proteome SARS-CoV-2. The involves temperature replica exchange sampling, making massively parallel...
This study investigated the effects of recurrent urinary tract infections (rUTI) and impact prophylaxis on rUTI patients' quality life (QoL).
In this paper, we propose to use hardware performance counters (HPC) detect malicious program modifications at load time (static) and runtime (dynamic). HPC have been used for characterization testing, system testing evaluation, as side channels. We HPCs static dynamic integrity checking of programs.. The main advantage HPC-based is that it almost free in terms cost; are built into all processors. overhead minimal because the operating checking, which called anyway process scheduling other...
Summary form only given. Parallel programming paradigms, over the past decade, have focused on how to harness computational power of contemporary parallel machines. Ease use and code development productivity, has been a secondary goal. Recently, however, there growing interest in understanding productivity issues their implications for overall time-to-solution. Unified C (UPC) is recently developed language which gaining rising attention. UPC holds promise leveraging ease shared memory model...
Hardware and software perspectives.
Traditional keyword based search is found to have some limitations.Such as word sense ambiguity, and the query intent ambiguity which can hurt precision.Semantic uses contextual meaning of terms in addition semantic matching techniques order overcome these limitations.This paper introduces a expansion approach using an ontology built from Wikipedia pages other thesaurus improve accuracy for Arabic language.Our outperformed traditional both F-score NDCG measures.
Modification to traditional SoC design flow can enable effective protection against maliciously inserted rogue functionality during and fabrication. This article presents a joint circuit-architecture-level approach that helps in preventing or detecting Trojan attacks.
Recent GPUs are equipped with general-purpose L1 and L2 caches in an attempt to reduce memory bandwidth demand improve the performance of some irregular GPGPU applications. However, due massive multithreading, suffer from severe resource contention low data-sharing which may degrade instead. In this work, we propose three techniques efficiently utilize caches. The first technique aims dynamically detect bypass accesses that show streaming behavior. second technique, dynamic warp throttling...
Mentions of the buzzword heterogeneous computing have been on rise in past few years and will continue to be heard for come, because is here stay. What computing, why it becoming norm? How do we deal with it, from both software side hardware side? This article provides answers some these questions presents different points view others.
This paper addresses the problem of chip level thermal profile estimation using runtime temperature sensor readings. We address challenges a) availability only a few sensors with constrained locations (sensors cannot be placed just anywhere) b) random on-chip power density characteristics due to unpredictable workloads and fabrication variability. Firstly we model as probability function. Given this characteristic readings, exploit correlation between dissipation different modules estimate...
In the beginning was single core ... Then we moved to multicore, before are fully ready for it! GPUs appear in scene, giving us very high performance some type of applications What is next? How can get more performance? The near future will be era heterogeneous computing. We already have a glimpse it now; you write code multicore and together, right? As computer systems become (cores different capabilities, GPUs, application specific hardware, ...), writing efficient becomes challenging....
A trusted platform module (TPM) enhances the security of general purpose computer systems by authenticating at boot time. Security can often be compromised due to presence vulnerabilities in software that is executed on system. Existing TPM architectures do not support runtime integrity checking and this allows attackers exploit these modify program after it has been verified (at time check or TOC) but before its use TOU) trigger unintended behavior, such as execution malicious code leaking...
Cache memories currently treat all blocks as if they were equally important. This assumption of important is not always valid. For instance, deserve to be in L1 cache. We therefore propose globalized block placement. present a global placement algorithm for managing cache hierarchy by deciding where the an incoming should placed. Our technique makes decisions adapting access patterns different blocks.
The simplification of space science and technology for students K–12 is a challenging task educators. Virtual reality augmented are educational techniques that introduce the concept games. Moreover, those have stunning effect on students. This work presents utilization virtual models to teach about satellite types, subsystems, assembly integration process, watching rocket launch carrying observing in its orbit laboratories. A 10-min mission laboratories will effectively improve learning...
This article addresses the problem of chip-level thermal profile estimation using runtime temperature sensor readings. We address challenges of: (a) availability only a few sensors with constrained locations (sensors cannot be placed just anywhere); (b) random chip power density characteristics due to unpredictable workloads and fabrication variability. Firstly we model as probability function. Given such statistical readings, exploit correlation in dissipation among different modules...
A Trusted Platform Module (TPM) authenticates general purpose computing platforms. This is done by taking platform integrity measurement and comparing it with a precomputed value at boot-time. Existing TPM architectures do not support run-time checking of program on the platform. Attackers can modify after has been verified Time Of Check (TOC) before its Use (TOU). In this paper we study feasibility integrating dynamic on-chip (DTPM) into core processor pipeline to protect against TOCTOU...
With hundreds of processing units in current state-of-the-art graphics (GPUs), the probability that one or more fail due to permanent faults, during fabrication post deployment, increases drastically. In our experiments we found loss a single streaming multiprocessor (SM) an 8-SM GPU resulted as much 16%performance loss. The default method for dealing with faulty SMs is turn them off. Although cannot be trusted completely execute kernel (program assigned SM) correctly, show can still make...
New trends in computer architecture include non-general purpose architectures, brain-inspired design, agile hardware development and environmentally responsible design. Computer Science students need to understand develop programs that can achieve high performance through a programmer's awareness of parallelism latency. In re-visit curriculum guidelines, could skills competencies less mature yet cutting-edge topics, including quantum computing. For example, should appreciate processor...
Abstract Since its invention, generative adversarial networks (GANs) have shown outstanding results in many applications. GANs are powerful, yet resource-hungry deep learning models. The main difference between and ordinary models is the nature of their output training instability. For example, can be a whole image versus other detecting objects or classifying images. Thus, architecture numeric precision network affect quality speed solution. Hence, accelerating pivotal. Data transfer...
Modern graphical processing units (GPUs) are equipped with general-purpose L1 and L2 caches to reduce the memory bandwidth demand improve performance of some irregular GPU (GPGPU) applications. However, due massive multithreading, GPGPU suffer from severe resource contention low data-sharing which may lead degradation instead. This paper proposes a low-cost streaming-aware conflict-avoiding thrashing-resistant (SACAT) cache management scheme that efficiently utilizes resources addresses all...