A review of the basic mechanisms affecting stability threshold voltage in response to a bias-temperature stress is presented terms charging and activation near-interfacial oxide traps. An energy approximately 1.1 eV was calculated based on new experimental results. Implications these factors, including recovery some stress-activated defects, for improved device reliability testing are discussed.

We have observed significant instability in the threshold voltage of 4H-SiC metal-oxide-semiconductor field-effect transistors due to gate-bias stressing. This effect has a strong measurement time dependence. For example, 20-mus-long gate ramp used measure I-V characteristic and extract was found result three four times greater than that measured with 1-s-long ramp. The V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> devices did not...

A comprehensive physical model for the analysis, characterization, and design of 4H-silicon carbide (SiC) MOSFETs has been developed. The verified an extensive range bias conditions temperatures. It incorporates details interface trap densities, Coulombic scattering, surface roughness phonon velocity saturation, their dependences on temperature. physics-based models were implemented into our device simulator that is tailored 4H-SiC MOSFET analysis. By using a methodology numerical modeling,...

Threshold voltage and drain current instabilities in state-of-the-art 4H-SiC MOSFETs with thermal as-grown SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> NO-annealed gate oxides have been studied using fast I-V measurements. These measurements reveal the full extent of instability underestimated by dc Furthermore, allow separation negative positive bias stress effects. Postoxidation annealing NO was found to passivate oxide traps...

Abstract This work reports on three important aspects of threshold-voltage instability in SiC power MOSFETs: (1) the bias-temperature observed commercial devices from two leading manufacturers, (2) a summary basic mechanisms driving this instability, and (3) need for an improved test method evaluating these devices. Even under significant overstress conditions, no negative shift was most-recent-vintage one manufacturers during −15 V, 175 °C negative-bias temperature stress lasting 120 h.

The interfacial region between silicon carbide (SiC) and its native oxide contains a high density of traps, which is considered major problem leading to lower mobility that has hindered SiC metal semiconductor field effect transistors from reaching their theoretical expectations. We investigate the microstructure chemistry 4H-SiC∕SiO2 interface due variations in nitric annealing aluminum implantation using Z-contrast imaging electron energy loss spectroscopy. A transition layer with carbon...

The application of existing reliability test standards, based on Si technology, to SiC power MOSFET qualification can in some cases result ambiguous results. Depending the exact measurement procedure, a given device stress tested under identical conditions may either pass or fail. large variations observed I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -V xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> characteristics, and...

Several important aspects related to the phenomena of ac gate-bias stress-induced threshold-voltage degradation in SiC MOSFETs are presented. These include a detailed investigation particular sensitivity trench-geometry devices when exposed negative overstress, specific conditions that drive this degradation, and its recovery by application dc bias temperature stress.

A two-way tunneling model describing simultaneous oxide trap charging and discharging in SiC MOSFETs is presented, along with a comparison experimental results. This can successfully account for the variation threshold-voltage instability observed as function of bias-stress time, magnitude, measurement time.

We have observed a significant increase in the instability of SiC power MOSFET ID-VGS characteristics following bias stressing at elevated temperature, similar to effect we previously an ON-state current stress. Devices stressed by temperature alone exhibited very little compared with devices both and applied bias. These results, along other results literature, suggest that this threshold voltage is due activation additional near-interfacial oxide traps related O-vacancy defect known as E′...

We have observed instability in the threshold voltage, VT, of SiC metal-oxide semiconductor field-effect transistors (MOSFETs) due to gate-bias stressing. This effect has routinely been by us all 4H and 6H MOSFETs from three different manufacturers—even at room temperature. A positive-bias stress, applying an electric field about 1 2 MV/cm across gate oxide, for 3 minutes followed a negative-bias stress another typically results shift ID-VGS current-voltage characteristic range 0.25 0.5 V is...

We have observed variations in the instability threshold voltage, VT, of SiC metaloxide semiconductor field-effect transistors (MOSFETs) from various sources and/or processes due to gate-bias stressing as a function temperature. In some cases we see dramatic increase with increasing temperature, consistent interfacial charge trapping or de-trapping. other temperature response is very slight, and still actually VT instabilities that move opposite direction bias, indicating presence mobile ions.

There are a number of potential reliability issues associated with SiC power MOSFETs, including threshold-voltage stability, gate-oxide reliability, body-diode robustness, short-circuit current and radiation effects. This work is primarily focused on stability the need for an improved test method to unambiguously separate out good devices from bad ones. Threshold-voltage affected by active charge traps in near-interfacial region insulating gate oxide. Their close proximity semiconductor...

A survey of methods for characterizing threshold voltage (VT) drift when applied to commercial SiC DMOSFETs was conducted explore how results can vary from one test another. Typical linear-with-log-stress-time VT observed with a rate increase near 50–60 mV/dec all methods. However, the magnitude varied greatly depending on time delay between stress and measurement. power law recovery ( ) common in much smaller drifts using slower methods, meaning long delays measurement lead tests that are...

A review of recent work on the effect threshold-voltage instability reliability SiC power MOSFETs is presented. Significant increases in ID-VGS characteristics due to ON-state current stressing are similar nature caused by high-temperature bias stressing. Devices stressed elevated temperature alone exhibited very little compared with devices both and applied bias. These results, along other results literature, suggest that this increase threshold voltage at activation additional...

Threshold voltage (Vt) stability of commercial SiC DMOSFETs during bias-temperature stressing was evaluated using the fast-Ic and fast Id-Vgs measurement techniques at both room elevated temperatures. Unipolar bias stress results confirmed that there is a rapid recovery Vt all vendors' devices showed same basic charge-trapping behavior, although some differences were observed in negative response high In situ measurements 10 kHz gate switching stable device operation temperature but...

Even with the successful introduction of SiC power MOSFETs into commercial market place, several key reliability issues have not been fully resolved. The main two are stability device threshold voltage, V T , and gate oxide. This work focuses on issue, which has investigated by a number different research groups in recent years [1-12].

We have analyzed the effect of post-oxidation nitride anneals (usually with either NO or N2O gases) on SiC MOSFETs. Two 4H:SiC wafers were identically prepared except that one wafer had a nitridation anneal after gate oxide was formed, while other tested as-oxidized. compared two processes by making measurements lateral MOSFETs and MOS capacitors using ID-VGS, C-V, charge pumping. There no change in flatband voltage interface trap density near valence band, suggesting net fixed remained...

One of the most important issues that limits performance and reliability SiC power MOSFETs is threshold voltage drain current instability under normal operation conditions. This phenomenon has been recently studied using conventional dc measurements. In this work, authors in state-of-the-art 4H-SiC fast I-V Fast measurements reveal full extent instability, underestimated by Furthermore, allow separation negative positive bias stress effects. Post oxidation annealing NO was found to passivate...

Although high-temperature measurements show a dramatic reduction in the bias-temperature stress-induced threshold-voltage instability of present state-of-the-art devices, more thorough test methodology shows that several different conclusions may actually be drawn. The particular conclusion depends on specific post-BTS measurement technique employed. Immediate room-temperature suggest significant oxide-trap activation still occurring. A significant, yet rapid, recovery is observed as well....

Since power devices such as DMOSFETs will operate at higher temperatures with accelerated degradation mechanisms, it is essential to understand the effects of typical operating conditions for electronics applications. We have found that SiC MOSFETs when gate-biased 150 °C show an increasing charge pumping current over time, suggesting interface traps (or perhaps near-interface oxide traps) are being created under these conditions. This trapping increase occurs slightly above...

Commercial SiC DMOSFETs were stressed at high temperatures by applying a switching bias waveform to the gate, frequency around 10 kHz (similar what standard gate driver would do in typical operating environment). Threshold voltage was monitored situ (without interruption of waveform) using fast I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> -V xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> measurement during pulse transitions....

This work presents an investigation of several important phenomena related to threshold-voltage instability in SiC MOSFETs. Such can occur previously unstressed as-processed devices, including trench-geometry when exposed a negative gate-bias overstress. also reports, for the first time MOSFETs, on dynamic nature ON resistance presence large instabilities, whether occurring devices or due ac stress-induced degradation.