Detecting layout hotspots is a key step in the physical verification flow. Although machine learning solutions show benefits over lithography simulation and pattern matching-based methods, it still hard to select proper model for large scale problems inevitably, performance degradation occurs. To overcome these issues, this paper, we develop deep framework high hotspot detection. First, use feature tensor generation extract representative features that fit well with convolutional neural...

While high-level synthesis (HLS) offers sophisticated techniques to optimize designs for area and performance, HLS-estimated resource usage timing often deviate significantly from actual quality of results (QoR) achieved by FPGA-targeted designs. Inaccurate HLS estimates prevent designers performing meaningful design space exploration without resorting the time-consuming downstream implementation process. To address this challenge, we first build a large collection C-to-FPGA diverse set...

With the continuous shrinking of technology nodes, lithography hotspot detection and elimination in physical verification phase is great value. Recently machine learning pattern matching based methods have been extensively studied to overcome runtime overhead problem expensive full-chip simulation. However, there still much room for improvement terms accuracy Overall Detection Simulation Time (ODST). In this paper, we propose a unified framework, where feature extraction optimization guided...

Triple Patterning Lithography (TPL) is widely recognized as a promising solution for 14/10nm technology node. In this paper, we propose an efficient layout decomposition approach TPL, with the objective to minimize number of conflicts and stitches. Based on our analysis actual benchmarks, found that whole can be reduced into several types small feature clusters, by some simplification methods, clusters solved very efficiently. We also present new stitch finding algorithm find all possible...

Mask optimization has been a critical problem in the VLSI design flow due to mismatch between lithography system and continuously shrinking feature sizes. Optical proximity correction (OPC) is one of prevailing resolution enhancement techniques (RETs) that can significantly improve mask printability. However, advanced technology nodes, process consumes more computational resources. In this paper, we develop generative adversarial network (GAN) model achieve better performance. We first an...

Mask optimization has been a critical problem in the VLSI design flow due to mismatch between lithography system and continuously shrinking feature sizes. Optical proximity correction (OPC) is one of prevailing resolution enhancement techniques (RETs) that can significantly improve mask printability. However, advanced technology nodes, process consumes more computational resources. In this article, we develop generative adversarial network (GAN) model achieve better performance. We first an...

Many competitive global routers adopt the technique of compressing 3D routing space into 2D in order to handle today's massive circuit scales. It has been shown as an effective way shorten time, however, quality will inevitably be sacrificed different extents. In this paper, we propose two techniques that directly operate on and can maximally utilize structure a grid graph. The first is called pattern routing, by which combine layer assignment, are able produce optimal solutions with respect...

In today's system-on-chip designs, both digital and analog parts of a circuit will be implemented on the same chip. Parasitic mismatch induced by layout affect performance significantly for designs. Consideration symmetry common centroid constraints during placement can help to reduce these errors. Besides two specific types constraints, other such as alignment, abutment, preplace, maximum separation, are also essential in placement. this paper, we present methodology that handle all at...

Detecting layout hotspots is one of the key problems in physical verification flow. Although machine learning solutions show benefits over lithography simulation and pattern matching based methods, it still hard to select a proper model for large scale inevitable that performance degradation will occur. To overcome these issues, this paper we develop deep framework high hotspot detection. First, feature tensor generation proposed extract representative features fit well with convolutional...

Typical standard cell placement algorithms assume that all cells are of the same height such can be aligned along rows. However, modern designs getting more complicated and multiple-row becomes common. With cells, not independent among different It turns out most commonly used detailed legalization techniques cannot extended easily to handle problem. We propose a novel algorithm in handling involving cells. The efficiently legalize local region with various heights, which is especially...

As the complexity and scale of FPGA circuits grows, resolving routing congestion becomes more important in placement. In this paper, we propose a routability-driven placement algorithm for large-scale heterogeneous FPGAs. Our proposed consists (1) partitioning, (2) packing, (3) global with estimation, (4) window-base legalization, (5) resource-aware detailed Experimental results show that our approach can give routable all benchmarks ISPD2016 contest achieve good result compared to other...

In this paper, we describe a routability-driven placer called Ripple. Two major techniques cell inflation and net-based movement are used in global placement followed by rough legalization step to reduce congestion. Cell is performed the horizontal vertical directions alternatively. We propose new method movement, which target position calculated for each considering of net as whole instead working on individually. detailed placement, use combination two kinds strategy: traditional...

Due to a significant mismatch between the objectives of wirelength and routing congestion, routability issue is becoming more important in VLSI design. In this paper, we present high quality placer Ripple 2.0 solve routability-driven placement problem. We will study how make use path information cell spreading relieve congestion with tangled logic detail. Several techniques are proposed, including (1) lookahead analysis pin density consideration, (2) path-based inflation (3) robust...

In this paper, we describe a routability-driven placer called Ripple. Two major techniques cell inflation and net-based movement are used in global placement followed by rough legalization step to reduce congestion. Cell is performed the horizontal vertical directions alternatively. We propose new method movement, which target position calculated for each considering of net as whole instead working on individually. detailed placement, use combination two kinds strategy: traditional...

Modern placement process involves global placement, legalization, and detailed placement. Global produce a solution with minimized target objective, which is usually wire-length, routability, timing, etc. Legalization removes cell overlap aligns the cells to sites. Detailed further improves by relocating cells. Since objectives like wire-length timing are optimized in legalization should not only minimize their own but also preserve solution. In this paper, we propose algorithm for...

As a good tradeoff between central processing unit (CPU) and application specific integrated circuit (ASIC), field-programmable gate array (FPGA) is becoming more widely used in both industry academia. The increasing complexity scale of modern FPGA, however, impose great challenges on the FPGA placement packing problem. In this paper, we propose RippleFPGA to solve simultaneously through set novel techniques: 1) smooth stair-step flow; 2) implicit similar ASIC legalization (LG); 3) two-level...

Detailed routing becomes a crucial challenge in VLSI design with shrinking feature size and increasing complexity. More complicated rules were added to guarantee manufacturability, which made detailed an even harder task achieve the flow. In this paper, we propose router that judiciously handles hard-to-access pins new including length-dependent parallel run length spacing, end-of-line spacing edges, corner-to-corner spacing. Our experimental results show our framework can effectively reduce...

The efficiency and effectiveness of many floorplanning methods depend very much on the representation geometrical relationship between modules. A good can shorten searching process so that more accurate estimations area interconnect costs be performed. Nonslicing floorplan is most general kind commonly used. Unfortunately, there not yet any complete nonredundant topological for nonslicing structure. In this paper, we propose first kind. Like some previous work (Zhou et al. 2001), have also...

As the complexity and scale of circuits keep growing, clocking architectures FPGAs have become more complex to meet timing requirement. In this paper, optimize wirelength meanwhile emerging architectural constraints, we propose several detailed placement techniques, i.e., two-step clock constraint legalization chain move. After integrating these techniques into our FPGA framework, experimental results on ISPD 2017 benchmarks show that proposed approach yields 2.3% shorter routed running time...

3-D chips rely on massive interconnect structures, i.e., large groups of through-silicon vias coalesced with multibit buses. We observe that wirelength optimization, a classical technique for floorplanning, is not effective while planning interconnects. This due to the interconnects' strong impact multiple design criteria like wirelength, routability, and temperature. To facilitate early progress massively-interconnected chips, we propose novel 3-D-floorplanning methodology which accounts...

Block Copolymer Directed Self-Assembly (DSA) is a promising technique to print contacts/vias for the 10nm technology node and beyond. By using hybrid lithography that cooperates DSA with multiple patterning, masks are used templates then can be guide self-assembly of block copolymer. In this paper, we propose approaches solve simultaneous template optimization mask assignment problem patterning. We verified in experiments our remarkably outperform state art work reducing manufacturing cost.

As VLSI technology nodes continue, the gap between lithography system manufacturing ability and transistor feature size induces serious problems, thus hotspot detection is of importance in physical verification flow. Existing approaches can be categorized into pattern matching-based machine learning-based. With extreme scaling growing complexity layout patterns, traditional methods may suffer from performance degradation. For example, have lower rates for unseen while learning-based lose...

Different from global routing, detailed routing takes care of many design rules and is performed on a significantly larger grid graph. In advanced technology nodes, it becomes the most complicated time-consuming stage in very large-scale integration physical flow. We propose Dr. CU, an efficient effective router, to tackle challenges. To handle 3-D graph enormous size, set two-level sparse data structures designed for runtime memory efficiency. For handling minimum-area constraint, optimal...

Recently the topic of routability optimization with prior knowledge obtained by machine learning techniques has been widely studied. However, limited prediction accuracy, predictors existing related works can hardly be applied in a real-world EDA tool without extra runtime overhead for feature preparation. In this paper, we revisit and propose practical plug-in named PROS which state-of-the-art commercial negligible overhead. consists an effective fully convolutional network (FCN) based...