A5005116115- VLSI and Analog Circuit Testing
- Integrated Circuits and Semiconductor Failure Analysis
- Radiation Effects in Electronics
- Low-power high-performance VLSI design
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- VLSI and FPGA Design Techniques
- Advancements in Photolithography Techniques
- Advanced Memory and Neural Computing
- Physical Unclonable Functions (PUFs) and Hardware Security
- Usability and User Interface Design
- Electron and X-Ray Spectroscopy Techniques
- Model-Driven Software Engineering Techniques
- Ferroelectric and Negative Capacitance Devices
- French Urban and Social Studies
- Engineering and Test Systems
- 3D IC and TSV technologies
- Manufacturing Process and Optimization
- Business Process Modeling and Analysis
- Cultural Insights and Digital Impacts
- Advanced Software Engineering Methodologies
- Information Technology and Learning
- Parallel Computing and Optimization Techniques
- Formal Methods in Verification
- Electronic Packaging and Soldering Technologies
Université de Montpellier
2016-2025
Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
2016-2025
Centre National de la Recherche Scientifique
2016-2025
École Nationale Supérieure de Mécanique et d'Aérotechnique
2010-2024
Safran (France)
2020-2024
Université de Poitiers
1979-2024
Institute of Electrical and Electronics Engineers
2022-2023
American Health Network
2022-2023
Antea Group (France)
2023
Institute of Computing Technology
2023
The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons and consequences increased during test. ends the opportunity to use such in varying situations.
The continuous advancement of complementary metal-oxide-semiconductor technologies makes flip-flops (FFs) vulnerable to soft errors. Single-node upsets (SNUs), as well double-node (DNUs), are typical This article proposes two radiation-hardened FF designs, namely DNU-tolerant (DUT-FF) and DNU-recoverable (DUR-FF). First, the DUT-FF which mainly consists four dual-interlocked-storage-cells (DICEs) three 2-input C-elements, is proposed. Then, provide complete self-recovery from DNUs, DUR-FF...
In advanced CMOS technologies, integrated circuits are sensitive to multiple-node-upsets (MNUs) induced in harsh radiation environments. The existing verification of the reliability latches highly relies on electronic design automation (EDA) tools considering complex error-injection scenarios. this paper, we propose a novel latch, namely MURLAV, protected against quadruple node-upsets (QNUs) environments, as well an algorithmic error-recovery method. latch provides complete recovery from all...
With the model of equivalent charge distribution, we calculated exact electrostatic force acting on real (conical) tip an atomic microscope. This applies to a conductive in front plane. We compared with several analytic models used date approximate forces and discussed their degree validity. estimated contribution cantilever total showed, basis theoretical calculations experimental results, that may constitute essential part range distances microscopy air.
Monitoring mixed-field radiation environments is of great importance especially for facilities hosting large particle accelerators. Such make use monitors that are usually composed different sensors, each one contributing to the evaluation levels throughout harsh zones and also effects over electronic devices. In this paper, we characterize our custom SRAM based according results retrieved by irradiating sensors at H4IRRAD test facility CERN. Based on collected upsets SRAMs using given...
In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. the context of information assurance through redundant design, this article proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against The mainly consists series mutually interlocked 3-input Muller C-elements (CEs) that forms circular structure. output any CE in respectively feeds back one...
Context:Optical interferometry is at a key development stage. ESO's VLTI has established stable, robust infrastructure for long-baseline general astronomical observers. The present second-generation instruments offer wide wavelength coverage and improved performance. Their sensitivity measurement accuracy lead to data images of high reliability. Aims:We have developed MATISSE, the Multi AperTure mid-Infrared SpectroScopic Experiment, access resolution imaging in spectral domain explore...
Aggressive technology scaling makes modern advanced SRAMs more and vulnerable to soft errors such as single-node upsets (SNUs) double-node (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled (QCCS) second Sextuple (SCCS). The QCCS cell comprises four cross-coupled input-split inverters keep stored values, provides self-recoverability from SNUs at low cost. To improve reliability, SCCS uses six construct a large error-interceptive feedback loop hence...
As semiconductor technologies scale down, radiative-particle-induced soft errors and static power consumption are becoming major concerns for digital circuits. Magnetic-tunnel-junctions (MTJs) widely used to address these concerns. MTJs nonvolatile (NV) compatible with traditional CMOS processes. In this article, we first propose a double-node-upset (DNU) tolerant NV latch, i.e., M-TPDICE-V2, providing high reliability. addition, further an advanced namely, M-8C, that is able completely...
The Von-Neumann memory wall bottleneck that keeps expanding is mainly caused by the frequent data transfer between main and processor. processing in-memory (PiM) capabilities of emerging nonvolatile devices have potential to partially alleviate problem. In this brief, we use ferroelectric field-effect transistor (FeFET), one devices, design a multifunctional cell, namely FeMPIM. It can perform multiple logic operations in computing mode as well content searching ternary content-addressable...
Quantum-dot cellular automata (QCA) is a novel nano-electronic technology. QCA has attracted wide attention due to its extremely small feature sizes at the molecular or even atomic scale and ultra-low power consumption, making it promising candidate replace complementary metal oxide semiconductor (CMOS) Binary-Coded Decimal (BCD) adders are widely used in industrial computing. In this brief, we propose two types of excess-3 code (XS-3) based BCD (XS-3DAs). We use ripple-carry (RCA) parallel...
During self-test, the switching activity of circuit under test is significantly increased compared to normal operation and leads an power consumption which often exceeds specified limits. In first part this paper, we propose a vector inhibiting technique tackles during operation. Next, mixed solution based on reseeding scheme proposed deal with hard-to-test circuits that contain pseudo-random resistant faults. From general point view, goal these techniques minimize total energy allow at...
Test power is now a big concern in large system-on-chip designs. In this paper, we present novel approach for minimizing consumption during scan testing of integrated circuits or embedded cores. The proposed low technique based on gated clock scheme the path and tree feeding path. idea to reduce rate cells shift operations without increasing test time. Numerous advantages can be found applying such technique.
In this paper, we present a new low power test-per-clock BIST test pattern generator that provides vectors which can reduce the switching activity during operation. The proposed power/energy technique is based on modified clock scheme for TPG and tree feeding TPG. Numerous advantages be found in applying such BIST.
With the rapid advancement of CMOS technologies, nano-scale latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely tolerate MNUs such as double-node upsets, triple-node upsets (TNUs), and even quadruple-node (QNUs). The is mainly constructed from three dual-interlocked-storage-cells (DICEs) triple-level soft-error interceptive module (SIM) consists six 2-input...
The continuous advancement of CMOS technologies makes SRAMs more and sensitive to soft errors. This paper presents two novel radiation-hardened SRAM cell designs, namely S4P8N S8P4N, with enhanced self-recoverability from single-node upsets (SNUs) Double-node (DNUs). First, the that has redundant nodes access transistors is proposed. following advantages: (1) it can self-recover all possible SNUs; (2) a part DNUs; (3) small overhead in terms power dissipation. Then, reduce read write time,...
This article proposes two quadruple node upset (QNU) recoverable latches, namely QNU-recoverable and high-impedance-state (HIS)-insensitive latch (QRHIL) QRHIL-LC (low-cost version of the QRHIL), for highly robust computing in harsh radiation environments. First, QRHIL that mainly consists a 5×5 looped C-element matrix is proposed. Then, to reduce overhead, uses 24 interlocking C-elements Both latches can self-recover from any QNU, while has low cost compared QRHIL. Simulation waveforms show...
In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple, quadruple node-upsets. Currently, verifications for error recovery of existing latches highly rely on EDA tools with complex error-injection combinations. this article, a latch design protected against MNUs in the harsh radiation as well an algorithm-based verification process is proposed. Due...
This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The proposed approach is based on a re-ordering vectors in test sequence to minimize switching activity circuit application. Our technique uses Hamming distance between and guarantees decrease consumption heat dissipation modifying initial fault coverage. Results experiments are presented at end this shows reduction range from 8.2 54.1%
Power consumption during scan testing is becoming a primary concern. In this paper, we present novel approach for cell ordering which significantly reduces the power consumed testing. The proposed based on use of two-step heuristic procedure that can be exploited by any chip layout program flip-flops placement and routing. works conventional design offers numerous advantages compared with existing low techniques. Reductions average peak are up to 58% 24% respectively experimented ISCAS...
High-quality at-speed scan testing, characterized by high small-delay-defect detecting capability, is indispensable to achieve delay test quality for DSM circuits. However, such testing susceptible yield loss due excessive power supply noise caused launch-induced switching activity. This paper addresses this serious problem with a novel and practical post-ATPG X-filling scheme, featuring (1) relaxation method, called path keeping X-identification, that finds don't-care bits from...