A5100455928- CCD and CMOS Imaging Sensors
- Infrared Target Detection Methodologies
- Image Processing Techniques and Applications
- Advanced DC-DC Converters
- Advanced Battery Technologies Research
- Analytical Chemistry and Sensors
- Transition Metal Oxide Nanomaterials
- Analog and Mixed-Signal Circuit Design
- Microgrid Control and Optimization
- Advanced Semiconductor Detectors and Materials
- Neuroscience and Neural Engineering
Shanghai University
2023
Delft University of Technology
2018
In this paper, we analyze the causes of nonlinearity a voltage-mode CMOS image sensor, including theoretical derivation and numerical simulation. A prototype chip designed in 0.18 μm 1-poly 4-metal process technology is implemented to verify analysis. The pixel array 160 × 80 with pitch 15 μm, it contains dozens groups pixels that have different design parameters. From measurement results, confirmed these factors affecting linearity can give guidance for future realize high sensor.
This paper presents a highly linear CMOS image sensor (CIS) designed in commercial 0.18-μm CIS technology. A new type of pixel is proposed based on the linearity analysis conventional 4T active pixel. The can mitigate nonlinearity caused by in-pixel source follower (SF) transistor. In addition, optimization design, digitally assisted calibration method to further reduce sensor, especially, integration capacitor (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
In this paper, different methodologies are employed to improve the linearity performance of a prototype CMOS image sensor (CIS). First, several pixel structures, including novel design based on capacitive trans-impedance amplifier (CTIA), proposed achieve higher pixel-level linearity. Furthermore, three types digital calibration methods explored. A designed in 0.18-μm, 1-poly, and 4-metal CIS technology with array 128×160 is used verify these improvement techniques. The measurement results...
This article focuses on the effect of operating temperature a CMOS image sensor (CIS) pixel performance, especially linearity behavior. As increases, value integration capacitor C FD in floating diffusion (FD) region increases as well. Moreover, gain in-pixel voltage buffer decreases. These two factors lead to reduced conversion gain. Due an increase nonlinear part FD, CIS at higher will deteriorate. A digital calibration method proposed previously is used improve CIS. Measurement results...
This paper presents two on-chip calibration methods for improving the linearity of a CMOS image sensor (CIS). A prototype 128 × pixel with size 10 μm×12 μm is fabricated using 0.18 1P4M CIS process. Both show obvious improvement on CIS. Compared voltage mode (VM) calibration, (PM) method achieves better results by nonlinearity 26×. in minimum 0.026%, which 2× than state-of-the-art.
Infrared sensors and focal plane imaging arrays are among the most important types of devices in field aerospace applications. To effectively amplify small signals collected by infrared for subsequent processing, a new multi-channel preamplifier circuit based on ultra-low temperatures was designed this study to read acquisition such devices. The technology an SMIC 180 nm CMOS with 1.8 V power adopted realize circuit. Meanwhile, eight-level adjustable gain switch used increase selectivity...