- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- Microwave Engineering and Waveguides
- Electromagnetic Compatibility and Noise Suppression
- Advanced Power Amplifier Design
- Semiconductor Quantum Structures and Devices
- Semiconductor Lasers and Optical Devices
- Analog and Mixed-Signal Circuit Design
- Semiconductor materials and devices
- Wireless Body Area Networks
- 3D IC and TSV technologies
- Antenna Design and Analysis
- Advanced Antenna and Metasurface Technologies
- Photonic and Optical Devices
- GaN-based semiconductor devices and materials
- Full-Duplex Wireless Communications
- Advancements in Semiconductor Devices and Circuit Design
- Millimeter-Wave Propagation and Modeling
- Energy Harvesting in Wireless Networks
- Advanced MEMS and NEMS Technologies
- Wireless Power Transfer Systems
- Cognitive Radio Networks and Spectrum Sensing
- Telecommunications and Broadcasting Technologies
- Bluetooth and Wireless Communication Technologies
- Advanced MIMO Systems Optimization
Kwangwoon University
2015-2024
Convergence
2014-2024
Analog Devices (United States)
2007
Toshiba (Japan)
2005
Samsung (United States)
2005
Market Matters
2003-2004
Qualcomm (United Kingdom)
2003-2004
University of California, Los Angeles
2001-2003
Daimler (Germany)
1998-2003
Samsung (South Korea)
1999-2002
Recent studies showed that conventional approaches being used to solve problems imposed by hard-wired metal interconnects will eventually encounter fundamental limits and may impede the advance of future ultralarge-scale integrated circuits (ULSls). To surpass these limits, we introduce a novel RF/wireless interconnect concept for inter- intra-ULSI communications. Unlike traditional "passive" interconnect, "active" is based on low loss dispersion-free microwave signal transmission,...
A fast and high-precision all-digital automatic calibration circuit that is highly suited for <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\Delta \Sigma$</tex></formula> fractional-N synthesizers designed to achieve a constant loop bandwidth lock time over an octave tuning range. high-speed frequency-to-digital converter (FDC) measures VCO frequency on-chip with sub- Notation="TeX">$f_{\rm...
A pseudo-exponential capacitor bank structure is proposed to implement a wide-band CMOS LC voltage-controlled oscillator (VCO) with linearized coarse tuning characteristics. An octave bandwidth VCO employing the 6-bit has been realized in 0.18-mum CMOS. Compared conventional binary weighted bank, considerably reduced variations of gain ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</i> <sub xmlns:xlink="http://www.w3.org/1999/xlink">VCO</sub>...
This work presents a Butler matrix based four-directional switched beamforming antenna system realized in two-layer hybrid stackup substrate for 28-GHz mm-Wave 5G wireless applications. The is composed of two layers with different electrical and thermal properties. It formed by attaching using prepreg, which the circuit components are placed both outer planes ground middle. upper layer that used as has εr = 2.17, tanδ 0.0009 h 0.254 mm. lower 6.15, 0.0028 By realizing array on lower-εr while...
This work presents an ultra-wideband conformal meandered loop antenna for wireless capsule endoscopy applications. The proposed surrounds the outer wall of a capsule, so that inner space can be used by battery and other electrical optical components. Fabricated on flexible substrate, has diameter 10 mm height 14 when wrapped around cylindrical capsule. achieves ultra-wide impedance bandwidth 200 MHz–2.05 GHz (164% fractional bandwidth), which provides sufficient coverage medical implant...
This work presents a 28-GHz Butler matrix based switched-beam antenna for fifth-generation (5G) wireless applications. It integrates 1 × 4 microstrip antenna, matrix, and single-pole four-throw (SP4T) absorptive switch in single planar printed circuit board is housed metal enclosure. Co-integration of packaged chip with the greatly enhances form factor integration level entire system. A wideband two-section branch line coupler employed to minimize phase magnitude errors variations matrix....
A 54-862-MHz single-chip CMOS transceiver with a single LC voltage-controlled oscillator (VCO) fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> synthesizer is developed for TV-band white-space communications and cognitive radio applications. The based on single-conversion zero-IF architecture integrated harmonic filtering capability. combined rejection mixer coarse RF tracking filter significantly lessens the in-band emission...
An active resistor-capacitor low-pass filter with simultaneously programmable high-end and low-end cutoff frequencies is presented for IEEE 802.22 cognitive radio transmitter applications. Transfer function analysis shows that the integrator frequency of a dc offset cancellation block should be tuned inversely proportional to open-loop gain maintain at constant value. Realized in 0.18- ¿m complementary metal-oxide-semiconductor, successfully between 740 Hz 10 kHz over 30-dB variation....
This paper presents a quadrature VCO that can be reconfigured between 6 and 9 GHz frequency bands. The dual-band comprises LC VCO, two 1/2-dividers, mixers, 3 notch filters. output is generated based on fractional multiplication method by mixing the with its divide-by-two signal. implemented in 0.18 /spl mu/m SiGe BiCMOS technology, shows fast switching time of 3.6 nsec. measured phase noises are -106 dBc/Hz -104 at 1 MHz offset for modes, respectively, while draining 10.8 mA from 1.8 V supply.
Full-duplex radio has potential to double spectral efficiency by simultaneously transmitting and receiving signals in the same frequency band, but at expense of additional hardware power consumption for self-interference cancellation. Hence, deployment a full-duplex cellular network can be realized employing functionality only an eNodeB, which is supposed have sufficient computation resources, scheduling pairs half-duplex UEs that are either downlink or uplink. By doing so, fast smooth...
본 논문에서는 5세대 이동통신을 위한 28 GHz 주파수 대역에서 스위치 빔포밍 안테나 시스템을 설계하였다. 시스템은 버틀러 매트릭스를 사용하였으며, 이는 다른 4 방향의 빔 조향을 할 수 있도록 각 출력단에 등간격의 위상을 생성한다. 배열 안테나는 원하는 4개의 방향으로 조향할 설계한 매트릭스는 커플러와 지연선로로 구성되며, 그 동작에 대하여 설명하였다. 유전율이 3이고, 5 mil의 높이를 가진 RO3003 기판을 이용하여 매트릭스의 사이즈는 <TEX>$20.3{\times}13.0mm^2$</TEX>이고, 안테나의 <TEX>$21.2{\times}19.9mm^2$</TEX>이다. <TEX>$-34^{\circ}{\sim}+33^{\circ}$</TEX>까지 있고, Sidelobe level(SLL)의 최소값은 12.9 dB이다. In this paper, a switched beamforming antenna system at frequency band is...
A technique to extract differential second harmonic output signals in a CMOS LC voltage-controlled oscillator (VCO) is introduced. In cross-coupled n-type field effect transistor (NFET) and p-channel (PFET) VCO topology, the upper lower common source nodes of FET pairs can provide well-balanced by resonating impedances at operating voltage-limited regime. The idea verified experimentally implementing 5.6-GHz having tunable impedance element node. error signal power between measured be -70dBm...
A CMOS single-chip transceiver IC is developed for IEEE 802.22 cognitive radio applications. Over the 54 to 862 MHz ultra wideband, in-band harmonic distortions of transmitter and unwanted mixing receiver are effectively suppressed by exploiting dual-path direct-conversion architecture. seamless coverage full band achieved employing a fractional-N PLL with single LC VCO multi-modulus LO generator. Implemented in 0.18 mum CMOS, achieves 110 dB gain dynamic range, < 8.5 noise figure, > -11 dBm...
A wideband complementary metal oxide semiconductor (CMOS) semidynamic frequency divide-by-3 covering more than two octave bandwidths is presented. The operation without requiring a quadrature signal source realized by employing three-stage RC polyphase filter. transfer function analysis on Type-II two- and filters performed to provide analytic solutions of the peak phase error attenuation. Implemented in 0.18 mum CMOS, operates over input range between 0.6 2.7 GHz while dissipating 15 mA...
This paper presents a direct-conversion zero-IF receiver front-end circuit for 28-GHz 5G mobile communications. The RF is composed of LNA, quadrature downconversion mixer, wideband 50-ohm driving buffer, and I/Q generation LO buffer. low-noise amplifier designed in two-stage, which the first cascode stage performs single-to-differential conversion by using transformer load. mixer gilbert-cell active type. buffer differential-to-single test interface purpose. An external signal fed to RC...
A low-power CMOS sliding-IF RF receiver is presented for Bluetooth Low Energy (BLE) applications. It comprises an LNA, mixer, transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) stage, IF transimpedance amplifier (TIA), and LO generation block. We present a comprehensive analysis of the second-order intermodulation (IM2) distortion that induced by in-band orthogonal frequency-division modulation (OFDM) blocker its...
A forward body biasing (FBB) technique is employed by an extended true-single-phase-clock (E-TSPC) divide-by-2 circuit in 0.25 mu m CMOS for efficient on-chip control of power and speed. By applying the bias voltage 0.4 V, maximum operating frequency improved 78% while current dissipation increased only 21%. As a result, divider figure-of-merit 46%. The phase noise however not significantly affected biasing. We believe that FBB can be means scaling speed E-TSPC RF circuits.
The second-order interaction effect in a field-effect transistor (FET) differential amplifier is analyzed using the Volterra series analysis method. results reveal that inherent fully structure, and thus can never be cancelled out. In contrast, it found possibly out by adding source degeneration impedance pseudodifferential (PDA) structure. addition, cancellation condition PDA made more robust wider over input signal swing adopting derivative superposition (DS) By combining technique DS...
We present a low-power CMOS active-resistance-capacitance (active-RC) complex bandpass filter (BPF) with tunable gain, bandwidth, center frequency, quality factor, and passband flatness for Bluetooth applications. A transfer function analysis cross-coupled Tow-Thomas biquad structure is presented to prove that the profile of gain can be effectively controlled by independently tuning two cross-coupling resistors. The proposed biquad-based BPF was employed realize fourth-order baseband analog...
A 2.7 Gb/s interconnect transceiver chip-set based on Code Division Multiple Access (CDMA) is described and implemented in 0.18 /spl mu/m CMOS technology to achieve real-time system re-configurability multiple I/O communication. The chip-set, with an Alexander-type multi-level data recovery circuit, can reconfigure signal routes within a symbol period of 0.8 ns. dissipates 74 mW occupies 0.3 mm/sup 2/ per pair.
A new push-push VCO architecture takes the second harmonic output signal from a capacitive common-node in negative-g/sub m/ oscillator topology. The generation of 2nd harmonics is accounted for by nonlinear current-voltage characteristic emitter-base junction diode causing; 1) significant voltage clipping and 2) different rising falling time during switching operation core transistors. prototype 12-GHz MMIC realized GaInP/GaAs HBT achieves an power -5 dBm, phase noise -108 dBc/Hz at 1 MHz...
Effects of forward body biasing (FBB) is investigated as an effective mean on-chip scaling power consumption and operating speed in CMOS true single phase clock (TSPC) RF frequency divide-by-2 circuits. Through extensive dc simulations 0.18 mum CMOS, the effects bias on threshold voltage, propagation delay, current dissipation are examined. Then, it shown that only with FBB voltage 0.2 V, circuits achieves 22% 21% improvements maximum while at cost 15% 32% more for TSPC extended (E-TSPC)...
Abstract A 2.4‐GHz bandpass filter is implemented on a flexible printed circuit board with thickness of 127 μm for wearable RF applications.The realized in double‐sided structure, which the top side provides main filtering characteristics using two coupled resonators and bottom efficient signal feeding coupling mixed scheme. The scheme combining broadside‐ cross‐coupling structures advantageous to improve insertion loss. when bended by up 90° are simulated three‐dimensional electromagnetic...
A CMOS driver amplifier employs two design techniques to improve its linearity in wide output power level. First, multiple-gated transistor (MGTR) technique with auxiliary transistors extends the linear region further compared MGTR single transistor. Second, resistive source degeneration significantly suppresses unwanted 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -harmonic feedback effect caused by an inductive degeneration....
A CMOS ultra-high frequency-band RF transceiver based on 8-phase harmonic rejection mixer (HRM) architecture with an integrated fractional-N PLL synthesizer is presented for television white space applications. divide-by-2 and a phase interpolator (PI) circuit are used to generate the LO signals HRM. The output frequency two times higher than desired band frequency. PI tunable allow 7-bit calibration of 45° 135° phases. systematic 2-D scheme that applicable both receiver transmitter...