Subramanian S. Iyer

ORCID: 0000-0003-1220-031X
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About
Contact & Profiles
Research Areas
  • Semiconductor materials and devices
  • 3D IC and TSV technologies
  • Advancements in Semiconductor Devices and Circuit Design
  • Electronic Packaging and Soldering Technologies
  • Semiconductor materials and interfaces
  • Semiconductor Quantum Structures and Devices
  • Advanced Memory and Neural Computing
  • Silicon Nanostructures and Photoluminescence
  • Integrated Circuits and Semiconductor Failure Analysis
  • Silicon and Solar Cell Technologies
  • Interconnection Networks and Systems
  • Thin-Film Transistor Technologies
  • Photonic and Optical Devices
  • Low-power high-performance VLSI design
  • Copper Interconnects and Reliability
  • Ferroelectric and Negative Capacitance Devices
  • VLSI and Analog Circuit Testing
  • Nanowire Synthesis and Applications
  • Neuroscience and Neural Engineering
  • Advanced Sensor and Energy Harvesting Materials
  • Silicon Carbide Semiconductor Technologies
  • Parallel Computing and Optimization Techniques
  • Advanced Surface Polishing Techniques
  • X-ray Diffraction in Crystallography
  • Crystallization and Solubility Studies

University of California, Los Angeles
2015-2024

Samueli Institute
2019-2024

University of California, San Diego
2024

UCLA Health
2021-2024

University of California System
2019

Eindhoven University of Technology
2019

Integra (United States)
2018

Bellingham Technical College
2018

Technical Design (United States)
2018

GlobalFoundries (United States)
2016

Advanced epitaxial growth techniques permit the use of pseudomorphic Si/sub 1-x/Ge/sub x/ alloys in silicon technology. The smaller bandgap these allows for a variety novel band-engineered structures that promise to enhance silicon-based technology significantly. authors discuss and properties then focus on their applications, especially x/-base heterojunction bipolar transistor (HBT). They show HBTs system allow decoupling current gain intrinsic base resistance. Such devices can be made by...

10.1109/16.40887 article EN IEEE Transactions on Electron Devices 1989-01-01

Strain compensation is an important aspect of heterostructure engineering. In this letter, we discuss the synthesis pseudomorphic Si1−yCy and Si1−x−yGexCy alloy layers on a silicon (100) substrate by molecular beam epitaxy using solid sources controlled strain that results from introduction ternary system. The C into substitutional sites in crystal lattice kinetically stabilized low-temperature growth conditions (400–550 °C) against thermodynamically favored silicon-carbide phases. constant...

10.1063/1.106774 article EN Applied Physics Letters 1992-06-15

The devices were fabricated using molecular-beam epitaxy (MBE), low-temperature processing, and germanium concentrations of 0, 6%, 12%. transistors demonstrate current gain, show the expected increase in collector as a result reduced bandgap due to Ge incorporation base. For 1000-AA base device containing 12% Ge, six-times was measured at room temperature, while 1000-times observed 90 K. temperature dependence Si/sub 0.88/Ge/sub 0.12/ transistor is consistent with shrinkage 50 meV....

10.1109/55.677 article EN IEEE Electron Device Letters 1988-04-01

In this growth process a new strain relief mechanism operates, whereby the SiGe epitaxial layer relaxes without generation of threading dislocations within layer. This is achieved by depositing on an ultrathin silicon insulator (SOI) substrate with superficial thickness less than thickness. Initially, thin Si put under tension due to equalization between and layers. Thereafter, created in plastic deformation. Since are formed glide layer, no dislocation ever introduced upper material, which...

10.1063/1.111778 article EN Applied Physics Letters 1994-04-04

Moore's law has so far relied on the aggressive scaling of CMOS silicon minimum features over 1000× for four decades, and recently, adoption innovative features, such as Cu interconnects, low-k dielectrics strained channels, high-k materials gate dielectrics, resulting in a better power performance, cost per function, density every generation. This spawned vibrant system-on-chip (SoC) approach, where progressively more function been integrated single die. The integration multiple dies...

10.1109/tcpmt.2015.2511626 article EN IEEE Transactions on Components Packaging and Manufacturing Technology 2016-02-25

Ordering in epitaxial Si/Ge alloys grown by molecular-beam epitaxy has been observed several authors. Attempts to explain this unusual phenomenon on the basis of bulk thermodynamic properties alloy have failed. In Letter we show that ordering is not an equilibrium property, but rather result surface growth kinetics. We attribute atomic-scale stresses present reconstructed Si(001) during growth, leading double-layer segregation Ge and Si along one four equivalent 〈111〉 directions. This...

10.1103/physrevlett.64.2038 article EN Physical Review Letters 1990-04-23

The influence of growth temperature on the interfacial abruptness strained Ge layers, a few monolayers thick, embedded in Si has been studied using Raman spectroscopy to identify presence GeGe and GeSi bonds medium energy ion scattering characterize spatial extent layers. Atomically sharp interfaces are observed for temperatures just above crystalline amorphous transition range, with pseudomorphic found >∼250 °C. Asymmetric mixing into capping layer occurs during at higher...

10.1063/1.101014 article EN Applied Physics Letters 1989-01-16

We find that heavy adsorbed dopant layers, up to several tens of equivalent monolayers, can be made produce heavily doped n (Sb) and p (Ga) layers in molecular beam epitaxy grown silicon. By preadjusting the adlayer concentration required value while temporarily arresting silicon growth, arbitrarily sharp profiles any sequence type with very high or low levels grown. Examples are given p+ i n++p+ pp+ structures transition thickness L?300 Å, controlled layer thicknesses ∼1000 Å. Such...

10.1063/1.329494 article EN Journal of Applied Physics 1981-09-01

We have synthesized pseudomorphic Si1−yCy (y≤0.05) alloys and strained layer superlattices on silicon by molecular beam epitaxy using solid sources for carbon silicon. The introduction of C into substitutional sites in the lattice is kinetically stabilized low-temperature growth conditions (500–600 °C) relatively high Si fluxes, against extremely low solubility (10−6 at 1420 thermodynamically favored carbide phases. Higher temperature leads to an islanded morphology. At lower temperatures,...

10.1063/1.106655 article EN Applied Physics Letters 1992-01-20

Since is perhaps the most attractive candidate for self‐aligned silicide technology, it important to understand high temperature process limitations of this material. Thin films are formed on single‐crystal silicon, or polysilicon, and, when annealed in He at temperatures 900°C higher, result degradation surface morphology and a drastic increase sheet resistance. Eventually, isolated agglomerates case annealing. In nitrogen annealing, they covered with . Shallow junctions thin layer top were...

10.1149/1.2108491 article EN Journal of The Electrochemical Society 1986-12-01

Crystal growth by molecular beam epitaxy (MBE) occurs under conditions of high supersaturation. The classic theory Burton, Cabrera, and Frank (BCF) is based on the assumption that surface steps move slowly. Consequently, it requires modifications to be applicable MBE because velocities may large. In addition, such are asymmetric structures, as observed experimentally field ion microscopy, capture probabilities from above below a step must differ markedly. Hence adatom concentration...

10.1147/rd.326.0804 article EN IBM Journal of Research and Development 1988-11-01

Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules. Thermal cycling stress results show no degradation of TSV or BEOL structures, device data indicate that there is significant impact from processing and/or proximity.

10.1109/iedm.2011.6131504 article EN International Electron Devices Meeting 2011-12-01

The scaling of package and circuit board dimensions is central to heterogeneous system integration. We describe our solderless direct metal-to-metal low pressure (<; 70 MPa) temperature 250 °C) thermal compression bonding (TCB) technique present preliminary results dielet (4 - 25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area) attach a rigid Silicon Interconnect Fabric (SiIF) with up two levels wiring (2 10 μm pitch). Dielets...

10.1109/ectc.2017.240 article EN 2017-05-01

Si0.5Ge0.5/Si superlattices and thick Si0.5Ge0.5 layers grown on (100), (111), (110) Si surfaces by molecular‐beam epitaxy (MBE) exhibit different growth morphologies defect structures. The best morphology is achieved (100) at low temperatures (∼400 °C), while thin defect‐free SiGe higher (∼600 °C) tend to undulated due the mismatch strain. Strained (111) are much more susceptible twin formation. a long‐range order along 〈111〉 directions. Our results indicate that such ordering occurs only...

10.1063/1.106083 article EN Applied Physics Letters 1991-10-28

We observe, for the first time, long-range order in thick, unstrained SiGe alloys, with and without boron doping. This ordering occurs along four equivalent 〈111〉 directions. The ordered domains are randomly shaped, corresponds to alternating double layers of Si Ge. Bond energy arguments used explain formation this new phase.

10.1103/physrevlett.64.40 article EN Physical Review Letters 1990-01-01

The authors present a high-quality dielectric system for use with Si/sub 1-x/Ge/sub x/ alloys. employs plasma-enhanced chemical vapor deposited (PECVD) SiO/sub 2/ on thin (6-8-nm) layer of pure silicon grown epitaxially the layer. buffer and oxide prevent accumulation Ge at oxide-semiconductor interface thus keep state density within acceptable limits. Si cap leads to sequential turn-on channel as is clearly observed in low-temperature C-V curves. show that this dual-channel structure can be...

10.1109/55.79571 article EN IEEE Electron Device Letters 1991-05-01

Pseudomorphic Si/Si-Ge strained layer superlattices are metastable and will relax to lower-energy, less strained, states on thermal annealing. Such relaxation may occur by the generation of misfit dislocation or compositional homogenization superlattice. The particular mechanism adopted is shown depend initial density structures. In cases where a significant portion strain accommodated an array dislocations in as-grown state there propensity generating additional dislocations. case...

10.1063/1.343245 article EN Journal of Applied Physics 1989-06-15

Single-phase SnxGe1−x alloys with x up to 0.3 have been grown by molecular beam epitaxy. X-ray diffraction measurements indicate the layers diamond crystal structure. The metastability of is apparent as increases in growth temperature, layer thickness, or Sn composition cause phase separation into a noncubic (white β-Sn) form. Rutherford backscattering spectrometry and reflection high-energy electron that initial stages are complicated. first several hundred angstroms compositionally graded,...

10.1063/1.101152 article EN Applied Physics Letters 1989-05-22

The apparent saturation of aggressive Moore's law scaling semiconductor technologies is pushing the boundaries traditional packaging and integration schemes to accommodate ever-growing data bandwidth heterogeneity demands. In this article, we demonstrate silicon-interconnect fabric (Si-IF) technology as a superior alternative conventional printed circuit boards (PCBs) enhance system scaling. Si-IF silicon-based, package-less, fine-pitch, highly scalable, heterogeneous platform assemble...

10.1109/tcpmt.2021.3075219 article EN IEEE Transactions on Components Packaging and Manufacturing Technology 2021-04-23

We report the first SiGe base heterojunction Bipolar Transistors (HBT) The devices were fabricated using Molecular Beam Epitaxy (MBE), low temperature processing and different germanium contents. transistors demonstrate current gain show expected increase in collector as a result of reduced bandgap due to Ge incorporation base. A 6 times was measured for 1000A device containing 12% Ge, consistent with shrinkage approximately 45 meV. For homojunction transistors, widths thin 800A grown,...

10.1109/iedm.1987.191578 article EN International Electron Devices Meeting 1987-01-01

Electrical fuse (eFUSE) has become a popular choice to enable memory redundancy, chip identification and authentication, analog device trimming, other applications. We will review the evolution applications of electrical solutions for 180 nm 45 technologies at IBM, provide some insight into future uses in 32 technology beyond with eFUSE as building block autonomic future.

10.1109/cicc.2007.4405850 article EN 2007-01-01

We have investigated the interaction between Ti and in temperature range of 400° to about 1000°C. The reaction proceeds a layer‐by‐layer fashion consists reduction followed by formation Ti‐rich silicide at interface. At higher temperatures, oxide is formed near surface. starts approximately 400°C, loss becomes significant above 500°C. A strong takes place 700°C above. thicker , resistance it has degradation due elevated effects.

10.1149/1.2115445 article EN Journal of The Electrochemical Society 1984-12-01
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