A5050351926- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Semiconductor Lasers and Optical Devices
- Photonic and Optical Devices
- Analog and Mixed-Signal Circuit Design
- Sparse and Compressive Sensing Techniques
- Advanced MEMS and NEMS Technologies
- Superconducting and THz Device Technology
- Acoustic Wave Resonator Technologies
- Advanced Frequency and Time Standards
- Electromagnetic Compatibility and Noise Suppression
- Thin-Film Transistor Technologies
- Advanced Sensor and Energy Harvesting Materials
- Microwave Imaging and Scattering Analysis
University of California, Los Angeles
2015-2017
This paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists triple-push Colpitts oscillators (TPCOs), followed by first second stage injection locking dividers (ILFDs) divide-by-16 chain. TPCOs are used to triple their fundamental frequencies 0.53-0.56 THz, while ILFDs subsequent divider chain divide such 2.7-2.9 GHz. back separate phase-locked loops with unique circuit designs accomplish...
The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution time-to-digital converter (TDC). Most TDC research in past focused on arrival time difference between edges divider feedback and reference signal [1-2]. This results coarser worse ADPLL performance. paper presents a fractional-/VADPLL that employs new conversion technique based sub-sampling phase detection. It accomplished directly sampling analog voltage at PLL's high frequency node converting it...
Spectra from 0.5 to 0.6THz play critical roles in planetary science, astrophysics and radio-astronomy as various chemical species including water, nitrates (NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , N O, NH xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) organics (CH xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> HCN) can either absorb or reflect radiation this frequency regime. Accordingly, NASA ESA have developed a...
Contactless (3D) touch sensors, when integrated with displays, offer many advantages over that of conventional touch-panel screens by offering a more hygienic and immersive & interactive human/machine interface for 3D user experiences [1]. While significant progress has been made in developing contactless sensors larger television monitor type displays [2-3], the technology yet to be infused into space- battery-constrained mobile devices (i.e., tablets smartphones). For successful insertions...
A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator noise, including supply-induced extracted from phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in domain. The receiver prototype fabricated 65nm CMOS technology achieves reduction −88 −109dBc/Hz at 1MHz offset, an integrated (IPN) −16.8 −34.6dBc, when operating 2.4GHz.
A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, accordingly adapts modulation scheme, data bandwidth carrier frequency. scheme ranges from NRZ/QPSK to PAM-16/256-QAM. highly re-configurable capable dealing low-cost cables/connectors or multi-drop buses deep narrow...
In this paper, a low overhead phase noise cancellation technique for ring oscillator (RO)-based quadrature receivers is presented. The proposed operates in background and extracts RO as well supply-induced from the digital phase-locked loop. obtained information then used to restore randomly rotated baseband signal domain. A receiver prototype fabricated standard 65-nm CMOS technology. It demonstrates reduction -88 -109 dBc/Hz at 1-MHz offset an integrated -16.8 -34.6 dBc when operating 2.4 GHz.
This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-timed pipeline two-stage SAR-binary-search architecture is proposed integrated with 4-GHz random-matrix clock generator, enabling physical speed up to 500 MS/s 40.2-dB SNDR in NS-mode an equivalent 4 GS/s 36.2-dB CS-mode, leading FOMs of 239 fJ/conversion-step 71 fJ/conversion-step, respectively. passive-charge-sharing open-loop...
A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a Σ-? fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) proposed delay line structure are constructed to provide on quantizetion noise. In the structure, dynamic element matching (DEM) techniques employed for linearization. The synthesizer fabricated 0.18-㎛ CMOS technology 2.14-㎓ output 4-㎐ resolution. die size 0.92 ㎜ × 1.15 ㎜, it consumes 27.2 ㎽. In-band phase noise...