A unified framework is presented in order to build lattice constellations matched both the Rayleigh fading channel and Gaussian channel. The method encompasses situations where interleaving done on real components or two-dimensional signals. In latter case, a simple construction of lattices congruent densest binary with respect Euclidean distance proposed. It generalizes, sense be clarified later, structural proposed by Forney (1991). These are next combined coset codes. partitioning rules...

A modified Gradient Descent Bit Flipping (GDBF) algorithm is proposed for decoding Low Density Parity Check (LDPC) codes on the binary-input additive white Gaussian noise channel. The new algorithm, called Noisy GDBF (NGDBF), introduces a random perturbation into each symbol metric at iteration. allows to escape from undesirable local maxima, resulting in improved performance. combination of heuristic improvements are and evaluated. When heuristics applied, NGDBF performs better than any...

This tutorial paper gives an overview of the implementation aspects related to turbo decoders, where term generally refers iterative decoders intended for parallel concatenated convolutional codes as well serial codes. We start by considering general structure and main features soft-input soft-output algorithm that forms heart decoders. Then, we show very efficient architectures are available all types allowing high-speed implementations. Other like quantization issues stopping rules used in...

Due to its high parallelism, belief propagation (BP) decoding is amenable high-throughput applications and thus represents a promising solution for the ultra-high peak data rate required by future communication systems. To bridge performance gap compared widely used successive cancellation list (SCL) algorithm, BP (BPL) polar codes extends candidate codeword exploration via multiple permuted factor graphs (PFGs) improve error-correcting of decoding. However, it significant challenge design...

This paper presents several techniques for the very large-scale integration (VLSI) implementation of maximum a posteriori (MAP) algorithm. In general, knowledge about Viterbi (1967) algorithm can be applied to MAP Bounds are derived dynamic range state metrics which enable designer optimize word length. The computational kernel is add-MAX* operation, add-compare-select operation with an added offset. We show that critical path reduced if reordered into offset-add-compare-select by adjusting...

A simplified algorithm for the check node processing of extended min-sum non-binary LDPC decoders is proposed. This novel technique, named bubble check, can reduce number compare operations by a factor three at elementary level. As this significant complexity reduction achieved without any performance loss, technique becomes highly attractive hardware implementation.

This paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on reduced-complexity version Extended Min-Sum algorithm. The main contributions this work correspond to variable node processing, codeword decision elementary check processing. Post-synthesis area show that is less than 20% Virtex 4 FPGA for decoding throughput 2.95 Mbps. implemented at 0.7 dB from Belief Propagation algorithm different code lengths rates. Moreover, proposed...

Through a rapid survey of the architecture low-density parity-check (LDPC) decoders, this paper proposes general framework to describe and compare LDPC decoder architectures. A set parameters makes it possible classify scheduling iterative memory organization, type check-node processors variable-node processors. Using proposed framework, an efficient generic for nonflooding schedules is also given.

A hardware white Gaussian noise generator (WGNG) is developed in an FPGA circuit for mobile communication channel emulation. High accuracy, fast and low-cost are reached by combining the Box-Muller central limit methods. The performance of designed model investigated using MATLAB. complexity level given some configurations show interest proposed model.

In this paper, a high accuracy Gaussian noise generator emulator is defined and optimized for hardware implementation on FPGA. The proposed based the Box-Muller method implemented by using ROM tabulation random memory access. By means of accumulations, central limit applied to output distribution. After presenting algorithmic method, paper analyzes its efficiency different signal formats. Then architecture fit into FPGA explained. Finally, results from synthesis are given show value implementation.

This paper deals with low-complexity algorithms for the check node processing in nonbinary LDPC decoders. After a review of state-of-the-art, we focus on an original solution to significantly reduce order complexity Extended Min-Sum decoder at elementary level. The main originality so-called Bubble Check algorithm is two-dimensional strategy processing, which leads reduction number comparisons. simulation results obtained show that this does not introduce any performance loss and it even...

Many of the current LDPC implementations DVB-S2, T2 or WiMAX standard use so-called layered architecture combined with pipeline. However, pipeline process may introduce memory access conflicts. The resolution these conflicts requires careful scheduling dedicated hardware and/or idle cycle insertion. In this paper, based on DVB-T2 example, we explain explicitly how can solve most two contributions paper are 1) to split matrix relax at a cost reduced maximum available parallelism 2) project...

This paper proposes a new soft-input soft-output decoding algorithm particularly suited for low-complexity high-radix turbo decoding, called local Viterbi (local SOVA). The SOVA uses the forward and backward state metric recursions just as conventional Max-Log-MAP does, produces soft outputs using update rules. proposed exhibits lower computational complexity than when employed in order to increase throughput, while having same error correction performance even used process. Furthermore,...

Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, the layered architecture not always straightforward because memory access conflicts in a-posteriori information memory. In this paper, we focus our attention on a particular type conflict introduced by existence multiple diagonal matrices DVB-T2 parity check matrix structure. We illustrate how reordering reduces number conflicts, at cost limiting level parallelism. then propose...

This brief presents an efficient architecture design for elementary-check-node processing in nonbinary low-density parity-check decoders based on the extended min-sum algorithm. relies a simplified version of bubble check algorithm and is implemented by means first-in-first-out. The adoption this new at node level results high-rate low-cost full-pipelined processor. A proof-of-concept implementation processor shows that proposed halves occupied field-programmable gate array (FPGA) surface...

This letter presents the mathematical framework involved in determination of an upper bound maximum spread value a D-dimensional turbo code frame size N. is named sphere (SB). It obtained using some simple properties Euclidian space (sphere packing finite volume). The SB for dimension 2 equal to /spl radic/2N. result has already been conjectured. For 3, we prove that cannot be reached, but can closely approached (at least up 95%). dimensions 4-6, construction particular interleavers shows...

A particular type of conflict due to multiple-diagonal sub-matrices in the DVB-S2 parity-check matrices is known complicate implementation layered decoder architecture. The new proposed DVB-S2X no longer use such sub-matrices. For implementing a compliant both with and DVB-S2X, we propose an elegant solution which overcomes these conflicts. relye on efficient write disable memories, allowing straightforward LDPC decoders. complexity latency are further reduced by eliminating one barrel...

In this letter, we present a Barrel-Shifter of size n extended by an additional layer that can handle any circular permutation on vector m, m ≤ n, thanks to specific initial positioning the data. The construction so-called Extended is motivated hardware decoder constraint related Low-Density Parity-Check (LDPC) code recently adopted for 5G mobile standard. proposed algorithm requires 42% less multiplexers than best state-of-the-art solution = 384 LDPC This proposal also able process several...

With the rapid size shrinking in electronic devices, radiation-induced soft-error has emerged as a major concern to current circuit manufacturing. In this paper, we present new error correction scheme based on residue number arithmetic cope with single issue. The proposed technique called bidirectional redundant system requires moduli satisfy some constraints achieve fast correction. system, both iterations for decoding valid and error-correcting table that contains all combinations of...