The increased resolution of Quad Full High Definition (QFHD) offers significantly enhanced visual experience. However, the corresponding huge data throughput up to 530 Mpixels/s greatly challenges design real-time video decoder VLSI with extensive requirement on both DRAM bandwidth and computational power. In this work, a lossless frame recompression technique partial MB reordering scheme are proposed save access QFHD chip. Besides, pipelining parallelization techniques such as...

Ultra high definition television (UHDTV) imposes extremely throughput requirement on video encoders based High Efficiency Video Coding (H.265/HEVC) and Advanced (H.264/AVC) standards. Context-adaptive binary arithmetic coding (CABAC) is the entropy component of these In very-large-scale integration implementation, CABAC has known difficulties in being effectively pipelined parallelized, due to critical bin-to-bin data dependencies its algorithm. This paper addresses encoding for UHDTV...

3840 × 2160 and 7680 4320 UHDTV formats deliver remarkably enhanced visual experience relative to high definition but in the meanwhile involve huge complexity memory bandwidth requirements video encoding. Especially, enlarged motion distances of lead additional difficulties implementation estimation, which is originally most critical bottleneck an encoder. This paper presents a estimation processor design for H.264/AVC. A test chip implemented 40 nm CMOS. With algorithm architecture...

8K Ultra HD is being promoted as the next-generation digital video format. From a communication channel perspective, latest high-efficiency coding standard (H.265/HEVC) greatly enhances feasibility of by doubling compression ratio. Implementation such codecs challenge, owing to ultra-high throughput requirements and increased complexity per pixel. The former corresponds up 10b/pixel, 7680×4320pixels/frame 120fps - 80× larger than 1080p HD. latter comes from new features HEVC relative its...

8K ultra-HD is being promoted as the next-generation video specification. While High Efficiency Video Coding (HEVC) standard greatly enhances feasibility of with a doubled compression ratio, its implementation challenge, owing to ultrahigh-throughput requirements and increased complexity per pixel. The latter comes from new features HEVC. At system level, most challenging them enlarged highly variable-size coding/prediction/transform units, which significantly increase requirement for...

8K×4K Super Hi-Vision (SHV) offers a significantly enhanced visual experience relative to 1080p, and is on its way being the next digital TV standard. In addition, advanced 3DTV specifications involving large number of camera views are targeted by emerging applications such as free-viewpoint (FTV). This paper presents single-chip design that supports real-time H.264 decoding SHV or up 32 HD views. The chip involved 3 key challenges: 1) Data dependencies video coding algorithms restrict...

An H.264/AVC HP video decoder is implemented in 90nm CMOS. Its maximum throughput reaches 4096×2160@60fps, which at least 4.3× higher than the state-of-the-art. By using partial MB reordering and lossless frame recompression, 51% of DRAM bandwidth reduced results 58% power saving. Meanwhile, various efficient parallelization techniques contribute to a core energy saving 54%.

This paper presents a high-performance context adaptive binary arithmetic coding (CABAC) architecture for the next-generation UHDTV applications. Its maximum throughput has been enhanced by 31%~34% with proposed pre-normalization (prenorm.), hybrid path coverage (HPC), bypass bin splitting (BPBS) and state dual-transition (SDT) schemes. Both HEVC H.264/AVC formats can be supported our applying dualstandard binarization design. The CABAC silicon proven in 65nm video encoder chip. It delivers...

In this paper, a highly parallel deblocking filter architecture for H.264/AVC is proposed to process one macroblock in 48 clock cycles and give real-time support QFHD@60fps sequences at less than 100MHz. 4 edge filters organized 2 groups simultaneously processing vertical horizontal edges are applied enhance its throughput. While parallelism increases, pipeline hazards arise owing the latency of data dependency algorithm. To solve problem, zig-zag schedule eliminate bubbles. Data path then...

Motion estimation and motion compensation in HEVC similar video codecs involve huge memory traffic storing loading reference frames. The resulting power composes a significant portion of system energy consumption. This paper presents reduction framework that losslessly compresses decompresses frames on-the-fly. We first present the architecture supports random access frame data compressed variable ratios. latest recompression algorithms corresponding VLSI implementation are also introduced....

An H.264/AVC intra-frame video encoder is implemented in 65 nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991 Mpixels/s for 7680×4320 p 60 fps video, 9.4× to 32× faster than previous designs. The also incorporates a 1.41 Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption achieved the high parallelism and hardware efficiency of this design. 1080p30 encoding dissipates only 2 mW at 0.8 V 9 MHz.

This paper presents an H.264/AVC intra-prediction design for ultrahigh definition (ultra-HD) video. Due to the huge throughput requirements of ultra-HD, challenges such as complexity and data dependency, which currently exist lower resolutions, become even more critical. To solve these problems, we first propose interlaced block reordering scheme together with a preliminary mode decision (PMD) strategy resolve dependency between intra reconstruction. In meantime, hardware cost is reduced by...

This paper presents a high-throughput decoder of HEVC context-based adaptive binary arithmetic coding (CABAC). A multi-sub-engine (MSE-AD) design is proposed to increase the average number bins delivered per clock cycle by adaptively processing different patterns upcoming with balanced critical path delay. syntax element (SE) grouping scheme maximize utilization MSE-AD under SE parsing order specified in standard. We also employ prediction-based pipeline alleviate data hazard problem. The...

This paper presents an efficient VLSI architecture of intra prediction for 8K×4K HEVC decoder. It supports all 35 modes and sizes ranging from 4×4 to 64×64. works proposed a Cyclic SRAM Banks based Parallel Reference Sample Fetching (CSB-PRSF), which guarantees enough reference samples reduces the number registers used storing samples. To guarantee high throughput, 16 pixels are predicted by Block Based Pipelining, dependency between neighboring blocks is eliminated Hybrid Data Forwarding...

This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 4k×2k encoding be achieved with negligible quality loss. 16×16 engine 8×8 work parallel for coefficients generating. A reordering interlaced reconstruction is also designed fully pipelined architecture. It takes only 160 cycles to process one...

This paper presents a new architecture for high performance intra prediction in H.264/AVC video coding standard, which can support H.264 profile features. Our goal is to design an Intra engine Ultra High Definition (UHD) Decoder (4Kx2K@60fps). The proposed achieve very stable throughput, process any modes within 66 cycles. Comparing with previous design, this feature guarantee the whole decoding pipeline work efficiently. overlap data preparing time and time, finish loading storing 2 cycles...

In this paper, we present a cache based motion compensation (MC) architecture for Quad-HD H.264/AVC video decoder. With the significantly increased throughput requirement, VLSI design MC is greatly challenged by huge area cost and power consumption. Moreover, long memory system latency leads to performance drop of pipeline. To solve these problems, three optimization schemes are proposed in work. Firstly, high-performance interpolator on Horizontal-Vertical Expansion Luma-Chroma Parallelism...

8K Ultra High Definition Television (UHDTV) requires extremely high throughput for video decoding based on H.265. In H.265, intra coding could significantly enhance compression efficiency, at the expense of an increased computational complexity compared with H.264. For prediction UHDTV real-time H.265 decoding, joint and issue is more difficult to solve. Therefore, divide-and-conquer strategy, we propose a new VLSI architecture in this paper, including two techniques, order achieve decoding....

As the successive video compression standard of H.264/AVC, High Efficiency Video Codec (HEVC) will play an important role in coding area. In deblocking filter part, HEVC inherits basic property H.264/AVC and gives some new features. Based on this variation, paper introduces a novel dual-mode architecture which could support both standards. For standard, proposed symmetric unified-cross unit (SUCU) based filtering scheme greatly reduces design complexity. result, processing 16×16 block needs...

In the latest video coding frameworks, efficiency of motion vector (MV) is becoming increasingly important because growing bit rate portion information. However, neither conventional median predictor, nor newer schemes such as minimum prediction scheme and hybrid scheme, can effectively eliminate local redundancy vectors. this paper, we present prioritized reference decision for efficient coding, based on H.264/AVC framework. This makes use a boolean indicator to specify whether predictor be...

This paper presents a new architecture for high profile intra prediction in H.264/AVC video coding standard. Our goal is to design an Intra engine 4Kx2K@60fps Ultra High Definition (UHD) Decoder. The proposed can provide very stable throughput, which predict any H.264 mode within 66 cycles. Compared with previous design, this feature guarantee the whole decoding pipeline work efficiently. divided into two parallel pipelines, one used 4x4 block loops and other prepare data MB loops. It...

This paper presents a new architecture for high performance intra prediction in H.264/AVC video coding standard. Our goal is to design an engine 4K×2K@60fps ultra definition (UHD) decoder. The proposed can provide very stable throughput, which process any H.264 modes within 66 cycles. Compared with previous design, this feature guarantee the whole decoding pipeline work efficiently. divided into two parallel pipelines, one used block loops and other prepare data MB loops. overlap preparing...

The first single-chip design that supports real-time H.264/Advanced Video Coding decoding of 8k (7680×4320) 60 frames/s is realized. It also multiview for up to 32720p views or 161080p views. To significantly improve the throughput and reduce memory bandwidth requirement, frame-level parallelism exploited proposed design. First, a frame dependency protection scheme enables frame-parallel decoding, by reusing multiple replicas an existing This results in system 2 Gpixels/s, at least 3.75...