It is shown that clock frequencies in excess of 200 MHz are feasible a 3- mu m CMOS process. This performance can be obtained by means clocking strategy, device sizing, and logic style selection. A precharge technique with true single-phase clock, which increases the frequency reduces skew problems, used. Device sizing help an optimizing program improves circuit speed factor 1.5-1.8. The depth minimized to one instead two or more, pipeline structures used wherever possible. Experimental...

An MOS transistor in silicon with 10−nm dioxide as gate insulator and palladium electrode was fabricated. The threshold voltage of this found to be a function the partial pressure hydrogen ambient atmosphere. At device temperature 150 °C it possible detect 40 ppm gas air response times less than 2 min.

We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability CMOS circuits at ground level and airplane flight altitudes. considered manufactured in a bulk process with lightly-doped p-type wafer. One method, based on empirical model, predicts linear decrease SER per bit decreasing feature size L/sub G/. A different MBGR even faster than linear. If increasing number bits is taken into account, then chip not expected to increase linearly

An n-channel MOS transistor with palladium gate was fabricated. The threshold voltage of this found to depend on the partial pressure hydrogen in ambient atmosphere. At a device temperature 150 °C, 10 ppm air is easily detected, and nitrogen or argon sensitivity considerably larger. A model, based adsorption palladium–silicon dioxide interface, proposed. This model explains behavior also able predict absolute for argon.

A field-effect transistor structure is used to study the transport properties of soluble conductive polymer, poly(3-hexylthiophene). We have measured conductance, mobility, and carrier concentration in undoped polymer thin films. The mobility was found be 10−5–10−4 cm2/V s at room temperature. decreases with increased change only partly reversible. Possible models are discussed.

The trading of speed for low power consumption in CMOS VLSI by using the supply voltage and threshold as variables was investigated. It is shown that it desirable to minimize minimizing consumption. lower bound possible decrease without loss were investigated under different circuit constraints, consequences performance calculated. Results show, example, reductions about 40 times can be obtained voltages down 0.48 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML"...

New dynamic, semistatic, and fully static single-clock CMOS latches flipflops are proposed. By removing the speed power bottlenecks of original true-single-phase clocking (TSPC) existing differential flipflops, both delays consumptions considerably reduced. For nondifferential best reduction factors 1.3, 2.1, 2.2, 2.4 for 1.9, 3.5, 3.4, 6.5 power-delay products with an average activity ratio (0.25), respectively. The total clocked transistor numbers decreased. In new clock loads minimized...

The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted. This class of circuits has the advantages simple distribution, small area for lines reduced skew problems, and high speed. Several examples are demonstrated.

A very important limitation of high-speed analog-to-digital converters (ADCs) is their power dissipation. ADC dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the ADCs, based on first principles and using pipeline flash architectures as examples. We find that high-resolution ADCs by noise, whereas technology limiting factor low-resolution devices. Our model assumes use digital error correction, but also study...

The properties of thin oxide MNOS structures are studied. An analytical theory for the switching time constant is derived and curves versus nitride field computed. These useful in design MNOS-memory transistors. compared with experiments. normal current assumed to be a modified Fowler-Nordheim current. At small thicknesses low field, an additional shown exist that attributed direct tunneling into traps nitride. discharge briefly discussed due charge carriers from semiconductor.

Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static has a major advantage: its superior noise margins. To be able to choose between static dynamic implementation of design, we need know the requirements logic. Here try identify possible errors, estimate limits discuss some solutions when considering in circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The near-sensor image processing concept, which has earlier been theoretically described, is here verified with an implementation. NSIP describes a method to implement two-dimensional (2-D) sensor array capacity in every pixel. Traditionally, there contradiction between high spatial resolution and complex processor elements, In the concept we have nondestructive photodiode readout can thereby process binary images without loosing gray-scale information. global handled by asynchronous Global...

It is shown that current transport through Schottky barriers formed by Pd on n-type silicon with a thin thermally grown oxide sensitive to hydrogen in the ambient. transition from minority- majority-carrier dominated occurs increasing pressure.

This paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC) downconversion (RFSD) filter, for WLAN applications in 2.4-GHz band. The RFSD filter test chip is fabricated 0.18-/spl mu/m CMOS technology and the measurement results show successful realization of sampling, quadrature downconversion, tunable anti-alias filtering, to baseband, decimation rate. By changing input rate, can be tuned different channels. A maximum rate 1072 MS/s has...

Abstract Field experiments were performed in artificial ponds to evaluate how the density of predatory diving beetles (Dytiscidae) would affect population levels mosquito larvae (Culicidae). Mosquitoes colonizing predominantly species genus Culex . In 2000, most dytiscids small ( Hydroporus spp.), and these predators had no impact on size larval populations, not even with added dytiscids. 2001, larger Ilybius, Rhantus , Agabus spp.) more common, there significantly fewer highest numbers...

Two of the main consequences advances in VLSI technologies are increased cost design and wiring. In CMOS synchronous systems, this is partly due to tedious synchronization different clock phases routing these signals. Here, a single-phase clocking scheme that makes very compact simple described. It shown general, simple, safe. provides structure can contain all components digital system, including static, dynamic, precharged logic as well memories PLAs. Clock data signals presented clean way...

A new model for dielectric loss, suitable time domain modeling of printed circuit boards, is proposed. The based on a physical relaxation model. Complete skin effect and losses in FR-4 boards are demonstrated experimentally verified. Finally, the developed used to predict that useful data rates up 10 Gb/s.

Vibrations of alkali-metal atoms adsorbed on a metal surface are observed by electron-energy-loss spectroscopy. From the loss intensity recorded for Na Cu(111) dynamic dipole charge 0.5e is obtained at low coverage. The found to decrease gradually with increasing coverage making peak due vibrations difficult observe coverages above approximately half full monolayer.

A number of recently reported CMOS line receivers and downconversion mixers are based on sampling. key component in these designs is the NMOS sampling switch. It can sample a very high bandwidth signal, several GHz for 0.8-/spl mu/m transistor. We present an expression aperture time switch when input has low swing. The can, under this condition, be modeled as device that determines weighted average over signal. weight function derived. shows maximum theoretical resolution standard 21 ps...