A5024622427- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Interconnection Networks and Systems
- Advanced Data Storage Technologies
- Experimental Learning in Engineering
- Algorithms and Data Compression
- Cloud Computing and Resource Management
- Distributed and Parallel Computing Systems
- Software-Defined Networks and 5G
- E-Learning and Knowledge Management
- Simulation-Based Education in Healthcare
- Educational Technology in Learning
- Liver Disease Diagnosis and Treatment
- Advanced Memory and Neural Computing
- Higher Education and Sustainability
- Higher Education Governance and Development
- Scheduling and Optimization Algorithms
- Design Education and Practice
- Medieval Iberian Studies
- Educational Research and Science Teaching
- Educational Innovations and Technology
- Higher Education Teaching and Evaluation
- Diet, Metabolism, and Disease
- Advanced Image and Video Retrieval Techniques
- Regional Development and Innovation
University of Córdoba
2004-2022
University of Carabobo
2013
Rationale: Metabolic syndrome (MetS) is a high-prevalence condition characterized by altered energy metabolism, insulin resistance, and elevated cardiovascular risk. Objectives: Although many individual single nucleotide polymorphisms (SNPs) have been linked to certain MetS features, there are few studies analyzing the influence of SNPs on carbohydrate metabolism in MetS. Methods: A total 904 (tag functional SNPs) were tested for 8 fasting dynamic markers performance an intravenous glucose...
This paper describes a new parallel sorting algorithm, derived from the odd-even mergesort named "partition and concurrent merging" (PCM). The proposed algorithm is based on divide-and-conquer strategy. First, data sequence to be sorted decomposed in several pieces that are using Quicksort. After that, all merged recursive procedure obtain final sequence. In each iteration of this pairs selected concurrently. analyzes computational complexity compares it with other well-known algorithms. We...
Cache memory is a common structure in computer system and has an important role microprocessor performance. A relationship between the performance of particular algorithm main cache parameters such as associativity, number words per block size been demonstrated. In this paper, we propose reconfigurable with several working modes. The was physically implemented on FPGA, connected to embedded processor tested for different algorithms, profiting configuration facilities these devices. test...
Nowadays, the computational systems (multi and uniprocessors) need to avoid cachecoherence problem. There are some techniques solve this The MESI protocol is one of them. This paper presents a simulator protocolwhich used for teaching cache memory coherence on computer withhierarchical system explaining process location inmultilevel systems. shows description course in which thesimulator used, short explanation about how simulatorworks. Then, experimental results real environment described.
As it is well known, teaching simulators are very useful resources to teach the practices of subjects and that students understand in a more optimal way theoretical concepts taught. Specifically, this work presents simulator, SICOME 2.0, which used Computer Architecture allows an interactive simulation on Simple Architecture. The also describes carried out subject with simulator. experience simulator satisfactory results obtained show helps improve comprehension subject.
Due to the COVID-19 pandemic and consequent restrictions, universities have had adapt their curricula substantially new schemes in which remote learning is of essence. In this study, we assess feasibility developing a mobile app supplementary distant teaching paradigm for “Cardiology” module “General Pathology” subject undergraduate Medical Education, evaluate its impact acceptability. A cohort volunteer second-year medical students (n = 44) access app, opinions on utility (1–10) were...
This paper presents a tool that simulates reconfigurable cache whose parameters can be changed at runtime through special instruction the ISA level. The was developed series of laboratory exercises in computer architecture. proposed system reconfigured within variety 298 combinations C, W and L (cache capacity, block size number blocks per set) without changing its students are introduced to hardware architecture while refreshing their knowledge on issues like digital design, register transfer level
The microprocessor performance is highly dependent on cache size and structure. This work presents a new design of reconfigurable implemented FPGA based previous work. Advantages the important enhancements are described analyzed. Experimental background tests carried out also discussed. Tests results favorable to in terms performance.
This paper presents a tool that simulates reconfigurable cache whose parameters can be changed at runtime through special instruction the set architecture (ISA) level. The proposed system reconfigured within variety of 298 combinations capacity, number ways or associativity, and line/block size in words (C, W, L) without changing its architecture. simulator was developed series laboratory exercises computer students are introduced to while refreshing their knowledge on issues like logic...
This paper presents the Web Evaluation Teaching Tool (WETT), a specifically created tool to survey students in order provide feedback about learning tools and methodologies. A performance example evaluation of two simulators is described.