An energy-efficient and multi-bit (4b) current-based analog compute in-memory (CIM) architecture is proposed in this paper. In CIM schemes, multiplication and-accumulate (MAC) operation performed on bitline, resultant output equivalent to bitline voltage drop <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\Delta \mathbf{V}_{\text{RBL}})$</tex> . However, dependence of xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta...

In this work, we propose an energy-efficient 64$\times $ 64 compute-in-memory (CIM) SRAM macro using a 7T bit-cell in 65nm CMOS UMC PDK. It supports 4-bit inputs, weights & outputs and performs MAC operations. also multiple row activations performing 1024 4b$\times $4b multiply accumulate (MAC) operations one clock cycle. Inputs are realized by the number of pulses on read wordline (RWL), which discharges bitline (RBL) according to bitwise multiplication inputs. Outputs 4 columns storing...

A robust, fully differential multiplication and accumulate (MAC) scheme for analog compute-in-memory (CIM) architecture is proposed in this article. The method achieves a high signal margin 4-bit CIM due to voltage changes on read bit-lines (RBL/RBLBs). achieved MAC operation 32 mV, which 1.14×, 5.82×, 10.24× higher than the state-of-the-art. robust against process, voltage, temperature (PVT) variations variability metric (σ/µ) of 3.64 %, 2.36× 2.66× lower reported works. has an...

An energy-efficient high signal margin analog compute-in-memory (CIM) architecture is proposed to support multi-bit multiplication and accumulate (MAC) operation. A transmission gate-based 10T SRAM bit-cell enhances the margin. The achieved 58 mV, 4.6× higher than state-of-the-art. metal-oxide-metal (MOM) C-2C capacitive bank provides better linearity of MAC achieves a throughput 128 GOPS. Furthermore, CIM density 32 GOPS/kb, 64× energy efficiency 36 TOPS/W, which 2.27× reported work....

In this brief, we present an energy-efficient and high compute signal-to-noise ratio (CSNR) XNOR accumulation (XAC) scheme for binary neural networks (BNNs). Transmission gates achieve a large signal margin (CSM) CSNR accurate XAC operation. The 10T1C SRAM bit-cell performs the in-memory operation without pre-charging larger bitline capacitances significantly reducing energy consumption per validation of proposed is done through post-layout simulations in 65nm CMOS technology with...

In recent years, there has been a growing demand for low-power devices, due to the fact that expansion of CMOS technology. Scale, crystal size corresponds SOC storage phenomenon, system-on-chip (SOC), decreased by number transistors increased. Overall, in on chip information is used various functions. They need economic, low energy consumption promote design capacity increase, power and little memory because it plays an important role growth overall device parameters playing tight leakage...

This brief uses the capacitive charge coupling method to present a multi-bit SRAM-based compute-in-memory (CIM) architecture in analog domain. The proposed consists of 64×64 9T1C SRAM array performing 1024 MAC operations between input activation (4-bit) and weight cycle, an optimized 4-bit Flash ADC is used for converting into digital output. work achieves throughput 455 GOPS energy efficiency 1012 TOPS/W at 222 MHz, maintaining very high signal margin 54 mV. achieved inference accuracy 98%...

This paper presents a switched capacitor-based 3C multiplier for multibit (4-b) multiplication and accumulation (MAC) operation in analog compute-in-memory (CIM) architecture. The proposed works on the principle of sequential charge sharing between three capacitors. has better area efficiency than state-of-the-art because it is independent from input bit precision N-bit MAC operation, requires only scheme achieves 1.12× improvement Figure-of-Merit (FoM) 4-b existing best state-of-the-art....

Achanakmar-Amarkantak Biosphere Reserve (A-A BR) is the 14th of country. It an interstate biosphere comprises major part Bilaspur district Chhattisgarh and with Anuppur Dindori districts Madhya Pradesh states. The a paradise faunal floral diversity. Recent survey made during rainy season in Amarkantak range under Forest Division Pradesh, buffer zone revealed occurrence 12 species butterflies (six belong to family Nymphalidae, two Pieridae, one belongs Danaidae, Erycinidae, Hesperiidae...

In Analog circuit design field, current reference is mostly used for constant supply to the circuits, so that their function runs properly.This work gives a operates with minimum operating voltage and current, CMOS generator presents its performance simulation in 180-nm UMC technology.The designed has four sub parts start-up, Bias-voltage, current-source sub-circuits, circuit, most of MOSFETs sub-threshold region.Simulation results shows 4-nA at 1 V line variation 0.203%/ܸ.It temperature...

In the field of power-aware applications, like smart sensors, wearable medical devices, required low supply voltage for operation.The should be insensitive to temperature variation and line power consumption in order few micro watts.To achieve this requirements a Nano-power CMOS circuit is designed.It generates constant reference output working with ranging from 0.8V 1.8V.Circuit was simulated UMC process.It generate 400mV at 0.8 V room temperature.A proper sub-threshold design operation...

This work depends on the principle of temperature compensation threshold voltage MOS transistor. It generates constant 333mV with supply range 0.8 V–1.3V. is implemented at 180nm in cadence EDA tool. The device has transistor circuits saturation and weak-inversion region. can 0.8V dc current consumption 0.5 μΑ room temperature. measured coefficient 0–150°C was 584ppm/°C. line Sensitivity 14%/V. (PSRR) −37 dB 100 Hz −45 10 MHz respectively.

This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with simulation in 180- nm UMC technology. The proposed consists of start-up, Bias-voltage, current-source sub-circuits most the MOSFETs operating sub-threshold region. Simulation results shows that generates stable 4-nA supply range 1 V- 1.8 V line sensitivity 0.203%/V.The temperature coefficient was 7592ppm/°C at 0°C-100°C. dissipation 380 NW Supply. would be suitable for use –operated...

A Nano power CMOS voltage generator circuit has been implemented using a 0.18μm standard process technology. The MOSFETs operated in sub threshold region without resistor. It works on the concept of temperature compensation voltage. generate 212mV output reference supply range 0.8–1.8V. coefficient was 256ppm/°C 0–150°C. line sensitivity 15%/V operating 0.8–1.8 V, and rejection ratio (PSRR) −42dB at 100 Hz −35dB 10 MHz.

This work depends on the principle of temperature compensation threshold voltage MOS transistor. It generates constant 509mV with supply range 0.7V - 1.8V. is implemented at 180nm in cadence EDA tool. The device has transistor saturation and weak-inversion mode. can dc current consumption <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.6 \mu\mathrm{A}$</tex> room temperature. measured coefficient 0–130 °C was 118ppm/°C. line Sensitivity...