Delta Sigma data converters employing high order dynamic element matching (DEM) allow for accurate signal conversion in the presence of DAC mismatch. However, at low oversampling rates, current DEM decoders provide little or no improvement error suppression over lower designs. In addition, logic requirement decoder increases significantly with each additional bit. This brief presents a that improves mismatch shaping performance to medium rates by up 15 dB, while methods reduce area overhead...

This paper presents SoCECT (system on chip embedded core test), a novel test controller architecture that allows multiple IEEE 1500 wrapped cores within SoC to be tested concurrently. makes use of the 1149.1 JTAG state machine operate and also allow for future integration with an P1687 interface. includes access mechanism (TAM) methodology(distributed architecture) reuses physical connections system bus provide efficient transport medium structural functional vectors between cores.

This paper presents design analysis and insights for a new continuous-time input pipeline (CTIP) analog-to-digital converter (ADC) architecture that has enhanced bandwidth. An all-pass filter-based analog delay in the signal path allows bandwidth extension to Nyquist bandwidths. A resetting integrator gain stage provides helping increase while reducing power cost. The noise filtering property of preserves medium resistive benefit CTIP ADCs. be implemented with feedforward compensated op-amp...

The relationship in electronics testing between the IEEE 1500 standard and 1149.1 standards is very close, where focuses on of boards embedded cores within system chips (SoC) boards. This paper presents a novel test controller architecture that facilitates control access to wrapped SoC using an port. based conventional state machine.

This paper presents a solution for implementing low-cost ADC BIST into System-on-Chip design. The is based on generating programmable ramp as test signal the and measuring linear parameters using histogram test. An original approach accurately Hits-per-Code traverses transfer curve presented. In particular, it shown that code transitions or flicker noise have an impact overall accuracy. procedure permits generator implementation engine design predominantly digital solution. Results...

The IEEE 1500 standard for embedded core test, approved in 2005, defines a scalable and reusable wrapper architecture that allows the testing of, access to, cores within system on chip (SoC). is controlled using Wrapper Instruction Register (WIR), has serial parallel ports test mechanisms (TAMs) to deliver vectors under test. In this study, authors consider two implementation challenges are outside standard: how multiple WIRs SoC accessed also TAM architecture. present novel solutions both...

An on-chip BIST solution performing accurate ADC measurements is presented. The platform enables linear and dynamic testing to occur in parallel, significantly lowering test time cost. On-chip hardware resources are optimized for application.

IEEE 1500 core wrappers supporting a hybrid scan mode provide for lower test times with minimal wiring and logic overheads. Wrapper vector formats that are easily integrated modern IC/FPGA design flows demonstrated.

This paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis equivalent unary-weighted topologies terms mismatch, noise, and output-impedance related distortion is carried out. From this analysis, we propose tri-level that achieves 12-bit static linearity suitable implementation ADC architecture. To reduce distortion, combines slice impedance matching with proposed compensation technique. By incorporating...

Direct Digital Synthesis (DDS) systems generate adjustable high resolution phase and frequency signals that are used in a wide variety of applications such as multi-mode RF, communications, measurements test. A performance band-pass DAC architecture implementation is presented delivers spectral purity over narrow-band response. The low power portable to standard CMOS processes achieves 110dB narrowband SFDR using sigma-delta (μΔ) modulation multi-bit current steering techniques. 3rd order...

This paper deals with the design and optimization of biquadratic switched capacitor filters for 4th order quadrature-mirror filter banks allowing real switch effects (e.g. on-state resistance, charge injection...) folded cascode OpAmp designed in 0.35 um CMOS technology. The is as a cascade two biquads each separately optimized using Differential Evolution Algorithm to obtain required transfer function deviation less than ±0.1 dB from function. process baseband signals (0 - 8 kHz) clock...

An optimal solution for implementing ADC built-in-self-test into a SOC design is presented. linear and dynamic testing occurs in parallel which reduces test time. A signal generator produces ramp histogram measurements sine-wave tests. This platform permits BIST that predominantly digital enables accurate using low silicon area.

A novel test controller architecture is presented that allows multiple IEEE 1500 wrapped cores within a SoC to be tested concurrently. The 1149.1 state machine used interface the allowing potential integration with emerging P1687 (IJTAG) standard. Also included access mechanism (TAM) methodology reuses physical connections of system bus provide an efficient transport medium for vectors between and cores.

Complexity in processor microarchitecture and the related issues of power density, hot spots wire delay, are seen to be a major concern for design migration into low nanometer technologies future. This paper evaluates hardware cost an alternative register-file organization, superscalar stack issue array (SSIA). We believe this is first such reported study using discrete elements. Several possible implementations evaluated, 90 nm standard cell library as reference model, yielding delay data...

This paper presents a stable 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> order mismatch shaping technique using vector feedback dynamic element matching (DEM). When combined with multi-bit sigma delta modulator, this DEM system allows high resolution band pass signals to be produced, low unary weighted DAC.

An Analog to Digital Converter Built-in-Self-Test design for System-on-Chip applications is presented. Linear and dynamic ADC test occur in parallel reduce overall time. A ramp generator used linear histogram measurements a sine-wave signal applied tests. The precisely measures Hits-per-Code enabling accurate linearity low-area optimal CPU operates measurements. Results demonstrate efficient silicon area overheads lower time capability.

IEEE 1500 test wrappers that enable higher bandwidth capability, system bus connectivity and efficient vector organization are presented. Embedded core vectors seamlessly work with ASIC FPGA design flows illustrated. Implementation test-chip show the positive impact on time potential for minimal wiring logic overhead savings.

This paper presents a processor architecture for Fast Fourier Transform computation of real-valued signals on-chip analog to digital converter test and evaluation. The design performs radix-2 technique optimized low area overhead easy integration into system on chips. hardware logic supports variable transform lengths accurate parameter extraction. has been validated 0.18um CMOS silicon applied data application extraction dynamic parameters that are SINAD, SFDR THD. is suitable...

This paper presents a design of low-latency 12-bit linear tri-level current-steering digital-to-analogue-converter for use in continuous-time ADCs. The DAC achieves static linearity, while the combination slice impedance matching with proposed compensation technique reduces output-impedance related distortion. demonstrates ~10dB improvement dynamic performance at high frequencies over Nyquist-band 100MS/ s. has been verified by simulation results TSMC 1.2V 65nm CMOS technology.

This paper presents a 6 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> order programmable bandpass dynamic-element-matching (DEM) that shapes the static mismatch error of Nyquist DAC for any choice center-frequency. The can be shaped over narrow or wide band, and up to 20% F <sub xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> depending on target application. work demonstrates 12-bit (5T-7B), lowest in-band SFDR IMD3 is 88dB 80dB...