A5007365958- Radiation Effects in Electronics
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- VLSI and Analog Circuit Testing
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Memory and Neural Computing
- Advancements in Battery Materials
- Integrated Circuits and Semiconductor Failure Analysis
Anhui University
2019-2020
In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. the context of information assurance through redundant design, this article proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against The mainly consists series mutually interlocked 3-input Muller C-elements (CEs) that forms circular structure. output any CE in respectively feeds back one...
In harsh radiation environments, nanoscale CMOS latches have become more and vulnerable to triple-node upsets (TNUs). This paper first proposes a latch design that can self-recover from any possible TNU for aerospace applications in the 16-nm technology. The proposed is mainly constructed seven mutually feeding-back soft-error-interceptive modules (SIMs), of which consists two three-input C-elements one two-input C-element. Due mutual feedback mechanism SIMs dual-level soft-error...
The continuous advancement of CMOS technologies makes SRAMs more and sensitive to soft errors. This paper presents two novel radiation-hardened SRAM cell designs, namely S4P8N S8P4N, with enhanced self-recoverability from single-node upsets (SNUs) Double-node (DNUs). First, the that has redundant nodes access transistors is proposed. following advantages: (1) it can self-recover all possible SNUs; (2) a part DNUs; (3) small overhead in terms power dissipation. Then, reduce read write time,...
This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) double-node (DNUs). First, the consisting of four input-split inverters is proposed. The achieves full SEU tolerance partial DNU through a feedback mechanism among its internal nodes. It also has low cost in terms area power dissipation mainly due to use only few transistors. Next, based on cell, QCCM12T proposed that uses extra access...
This paper presents a single-event double-upset (SEDU) self-recoverable and transient (SET) pulse filterable latch design for low power applications in 22nm CMOS technology. The mainly consists of eight mutually feeding back C-elements Schmitt trigger. Simulation results have demonstrated both the SEDU self-recoverability SET filterability using redundant silicon area. Using clock gating technology, saves about 54.85% dissipation on average compared with up-to-date designs which are not at all.
In this paper, a highly reliable SRAM cell, namely SESRS is proposed. Since the cell has special feedback mechanism among its internal nodes and more access transistors compared to standard provides following advantages: (1) it can self-recover from single node upsets (SNUs) double-node (DNUs); (2) reduce power consumption by 49.78% silicon area 7.92%, with only existing which all possible DNUs. Simulation results validate robustness of proposed cell. Moreover, state-of-the-art hardened...
The Aggressive technology scaling makes modern advanced SRAMs more and sensitive to soft errors that include single-node upsets (SNUs) double-node (DNUs). This paper presents a novel Sextuple Cross-Coupled SRAM cell, namely SCCS which can tolerate both SNUs DNUs. cell mainly consists of six cross-coupled input-split inverters, constructing large error-interceptive feedback loop robustly retain stored values. Since the has many redundant storage nodes, achieves following robustness: (1)...
In this paper, a novel self-recoverable SRAM cell, namely SRS14T is proposed in 22nm CMOS technology. Since the cell has special feedback mechanism among its internal nodes and more access transistors, provides following advantages: (1) It can self-recover from single node upsets (SNUs) partial double-node (DNUs); (2) it reduce time power consumption. Simulation results validate robustness of cell. Moreover, compared with state-of-the-art hardened cells, read time, write dissipation by...