We have designed, fabricated, and tested a prototype mixed-signal, 28×28-binary-input, 10-ouput, 3-layer neuromorphic network based on embedded nonvolatile floating-gate cell arrays redesigned from commercial 180-nm NOR flash memory. Each array performs very fast energy-efficient analog vector-by-matrix multiplication, which is the bottleneck for signal propagation in networks. All functional components of circuit, including 2 synaptic with 101,780 cells, 74 neurons, peripheral circuitry...

Potential advantages of analog- and mixed-signal nanoelectronic circuits, based on floating-gate devices with adjustable conductance, for neuromorphic computing had been realized long time ago. However, practical realizations this approach suffered from using rudimentary cells relatively large area. Here, we report a prototype $28\times28$ binary-input, ten-output, three-layer network arrays highly optimized embedded nonvolatile cells, redesigned commercial 180-nm nor flash memory. All...

Mixed-signal hardware accelerators for deep learning achieve orders of magnitude better power efficiency than their digital counterparts. In the ultra-low consumption regime, limited signal precision inherent to analog computation becomes a challenge. We perform case study 6-layer convolutional neural network running on mixed-signal accelerator and evaluate its sensitivity specific noise. apply various methods improve noise robustness demonstrate an effective way optimize useful ranges...

High-precision individual cell tuning was experimentally demonstrated, for the first time, in analog integrated circuits redesigned from a commercial NOR flash memory. The is fully automatic, and relies on write-verify algorithm, with optimal amplitude of each write pulse determined runtime measurements, using compact model cell's dynamics, fitted to experimental results. algorithm has allowed 100-cell array any desired state within 4-orders-of-magnitude dynamic range. With 10 pulses,...

The 3-D NAND flash memory has become an integral part of the cyber-physical systems to cope with huge data explosion in this era Internet Things (IoT). Moreover, hardware security primitives such as physical unclonable function (PUF) have indispensable functional circuits these for protection against vulnerabilities and adversary attacks. Therefore, paper, first time, we propose a PUF exploiting intrinsic variability string current ubiquitous owing process variations inherent material...

We propose combination of "dropout" and "Manhattan Rule" training algorithms for memristive crossbar neural networks to reduce circuit area overhead in-situ training. Using accurate phenomenological model devices, we show that such allows achieving 0.7% misclassification rate on the MNIST benchmark, which is comparable best reported results. At same time, considered approach reducing size memory circuits, largest component, required store intermediate weight adjustments during training, by...

We have designed, fabricated, and successfully tested a prototype mixed-signal, 28x28-binary-input, 10-output, 3-layer neuromorphic network ("MLP perceptron"). It is based on embedded nonvolatile floating-gate cell arrays redesigned from commercial 180-nm NOR flash memory. The allow precise (~1%) individual tuning of all memory cells, having long-term analog-level retention low noise. Each array performs very fast energy-efficient analog vector-by-matrix multiplication, which the bottleneck...

Passively-integrated memristors are the most prospective candidates for designing high-speed, energy-efficient, and compact neuromorphic circuits. Despite all promising properties, experimental demonstrations of passive memristive crossbars have been limited to circuits with few thousands devices until now, which stems from strict uniformity requirements on <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IV</i> characteristics memristors....

The progress in neuromorphic computing is fueled by the development of novel nonvolatile memories capable storing analog information and implementing neural computation efficiently. However, like most other circuits, these devices circuits are prone to imperfections, such as temperature dependency, noise, tuning error, etc., often leading considerable performance degradation network implementations. Indeed, imperfections major obstacles path further ultimate commercialization technologies....

Mixed-signal hardware accelerators for deep learning achieve orders of magnitude better power efficiency than their digital counterparts. In the ultra-low consumption regime, limited signal precision inherent to analog computation becomes a challenge. We perform case study 6-layer convolutional neural network running on mixed-signal accelerator and evaluate its sensitivity specific noise. apply various methods improve noise robustness demonstrate an effective way optimize useful ranges...