A5012094754- VLSI and FPGA Design Techniques
- Advanced Multi-Objective Optimization Algorithms
- Analog and Mixed-Signal Circuit Design
- Particle Detector Development and Performance
- Particle physics theoretical and experimental studies
- Radiation Detection and Scintillator Technologies
- CCD and CMOS Imaging Sensors
- Neural Networks and Applications
- Muscle activation and electromyography studies
- Advanced Memory and Neural Computing
- Business and Management Studies
- Evolutionary Algorithms and Applications
- Low-power high-performance VLSI design
- Social and Economic Solidarity
- Innovative Teaching Methods
- Neurotransmitter Receptor Influence on Behavior
- Hand Gesture Recognition Systems
- High-Energy Particle Collisions Research
- Advancements in Semiconductor Devices and Circuit Design
- Smart Cities and Technologies
- Occupational Health and Safety Research
- 3D IC and TSV technologies
- Smart Agriculture and AI
- Data Mining Algorithms and Applications
- Human Mobility and Location-Based Analysis
Universidade Federal do Rio Grande do Sul
2012-2024
Hospital Universitário da Universidade de São Paulo
2024
Universidade de São Paulo
2011-2020
Universidade Federal de Santa Catarina
2018-2020
Pontifícia Universidade Católica do Rio Grande do Sul
2016
Association of the Technological Integrated Systems Laboratory
2013
This paper presents the test results of second prototype SAMPA, ASIC designed for upgrade read-out front end electronics ALICE Time Projection Chamber (TPC) and Muon (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply provides 32 channels, selectable input polarity, three possible combinations shaping time sensitivity. Each channel consists Charge Sensitive Amplifier, semi-Gaussian shaper 10-bit ADC; Digital Signal Processor digital filtering compression...
This paper presents the SAMPA, an ASIC designed for upgrade of read-out front end electronics ALICE Time Projection Chamber (TPC) and Muon Chambers (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply includes 32 channels, selectable input polarity, five possible combinations shaping time sensitivity. Each channel comprises Charge Sensitive Amplifier, semi-Gaussian shaper 10-bit ADC, followed by Digital Signal Processor. A prototype multi project run was...
Conseil Européen pour la Recherche Nucléaire is currently undergoing a major upgrade within the A Large Ion Collider Experiment (ALICE) detectors, one of four main experiments at Hadron (LHC) accelerator. The LHC luminosity will increase making heavy ions collision rate rise from 500 Hz to 50 kHz. Both time projection chamber (TPC) and muon (MCH) detectors demand new faster readout electronics, which support continuous cope with this higher rate. This paper presents serialized analog-digital...
Speaking and presenting in public are critical skills for academic professional development. These demanded across society, their development evaluation a challenge faced by higher education institutions. There some challenges to evaluate objectively, as well generate valuable information professors appropriate feedback students. In this paper, order understand detect patterns oral student presentations, we collected data from 222 Computer Engineering (CE) fresh students at three different...
This paper presents a method for analog design synthesis at circuit-level and pareto front exploration of the through combined approach Simulated Annealing (SA) Particle Swarm Optimization (PSO). The consists dividing parameters search in three main parts. first has objective finding minimal specifications defined by user use SA using an aggregate function to combine all objectives into single cost function. second part starts when specs are met it performs single-objective optimization each...
Neural networks are achieving state-of-the-art performance in many applications, from speech recognition to computer vision. A neuron a multi-layer network needs multiply each input by its weight, sum the results and perform an activation function. This paper presents variation of implementation amplifier-based MOS analog capable performing these tasks also optimization synaptic weights using in-loop circuit simulations. transistors operating triode region used as variable resistors convert...
This paper presents a technique for performing analog design synthesis providing fast feedback the designer through reduced exploration of pareto frontier. Simulated Annealing is used as optimization algorithm and piecewise linear functions are single-objective cost in order to produce smooth equal convergence all measurements desired specifications on multi-objective function. After minimum met, performed each objective obtain non-exhaustive The results filtered solutions then re-filtered...
The design of analog integrated circuits is a demanding task that involves many constraints and objectives. Also, the transistor models employed must consider high-order physics effects to achieve accurate solutions. Geometric Programming (GP) allows finding global minimum in optimisation problems, but requires equations be monomial or posynomial form. This work proposes simplified model inspired on Advanced Compact MOSFET tailored used GP problems. proposed considers short-channel it valid...
This paper proposes a method that combines hardware description language and Random Forests theory, to develop motion recognition embedded system. To validate this system, the Ninapro database DB2 was used as training test data, resulting in an accuracy of 83.1% for base movement prediction.
This paper approaches the problem of analog circuit synthesis through use a Simulated Annealing algorithm with capability performing crossovers past anchor solutions (solutions better than all others in one specifications) and modifying weight Aggregate Objective Function specifications order to escape local minimums. Search for global optimum is followed by search Pareto front, which represents trade-offs involved design it performed using proposed together Particle Swarm Optimization. In...
This paper presents the accurate synthesis of a narrow-band CMOS Low Noise Amplifier (LNA) using an optimization-based approach. Multi-objective information and corners fabrication process are used in synthesizer to simultaneously optimize impedance matching, performance parameters circuit robustness. The approach combines Simulated Annealing algorithm with crossover operator automatic weight adjustment technique. combination allows optimizer escape local minimums therefore successfully...
The present paper describes a sequential pattern mining based approach to identify the main corporal sequences in students oral presentations during given course. Data from was collected through use of Microsoft Kinect and blind software, total number observations 65. 7 features were used as input information SPMF tool, allowing identification presenters. Sequences with Hands Down attribute most frequent all presentations. It has also been found that 1 3 are more similar terms sequence than...
The quality control is an essential step in fabric industries. Detectdefects the early stages can reduce costs and increase qualityof products. Currently, this task mainly done by humans,whose judgment be affected fatigue. Computer vision-basedtechniques automatically detect defects, reducing need forhuman intervention. In context, work proposes imageblock-processing approach, where we compare Segmentation-Based Fractal Texture Analysis, Gray Level Co-Occurrence Matrix,and Local Binary...