A5103074938- Electrowetting and Microfluidic Technologies
- Modular Robots and Swarm Intelligence
- Parallel Computing and Optimization Techniques
- Biosensors and Analytical Detection
- Low-power high-performance VLSI design
- Embedded Systems Design Techniques
- Advanced Data Storage Technologies
- VLSI and FPGA Design Techniques
- Photonic and Optical Devices
- Software System Performance and Reliability
- Ferroelectric and Negative Capacitance Devices
- Cloud Computing and Resource Management
- Microfluidic and Capillary Electrophoresis Applications
- Data Stream Mining Techniques
- Peer-to-Peer Network Technologies
Intel (United States)
2023
University of California, Riverside
2012-2018
CPUs and dedicated accelerators (namely GPUs FPGAs) continue to grow increasingly large complex support todays demanding performance power requirements. Designers are tasked with evaluating the of similarly design spaces during pre-silicon for reduce time-to-market limit manufacturing costs, or figure out how best map applications onto FPGAs using high-level synthesis tools. Typically, cycle-accurate simulators used evaluate workloads avoid overhead place-and-route when targeting FPGAs;...
Synthesis of digital microfluidic biochips (DMFBs) is a crucial to the advancement and realization miniaturized, automated, programmable biochemistry solutions; synthesis performed in three steps: scheduling, placement routing. In principle, algorithms for specific steps should be interchangeable with one another; however, different research groups typically develop each step isolation from another. Thus, it difficult compare against another, or determine which share synergies. We introduce...
FPGA application developers must explore increasingly large design spaces to identify regions of code accelerate. High-Level Synthesis (HLS) tools automatically derive FPGA-based designs from high-level language specifications, which improves designer productivity; however, HLS tool run-times are cost-prohibitive for space exploration, preventing designers adequately answering cost-value decisions without expert guidance. To address this concern, paper introduces a machine learning framework...
We introduce a Force-directed List Scheduling (FDLS) algorithm for resource-constrained assay compilation targeting Digital Microfluidic Biochips (DMFBs). This has been used in the past high-level synthesis of digital signal processing systems, and is now applied to DMFB synthesis. The results show improvements compared (LS) Path (PS), most efficient heuristics that have proposed, date, DMFBs. FDLS was also competitive with longer-running iterative improvement scheduling algorithms based on...
Digital microfluidics based on electrowetting-on-dielectric technology is poised to revolutionize many aspects of chemistry and biochemistry through miniaturization, automation, software programmability. microfluidic biochips (DMFBs) offer ample spatial parallelism, which then exposed the compiler. The first problem that a DMFB compiler must solve resource-constrained scheduling, NP-complete. If applied off-line, long-running algorithms produce solutions high quality, such as iterative...
This paper introduces a predictive modeling framework to estimate the performance of GPUs during pre-silicon design. Early-stage prediction is useful when simulation times impede development by rendering driver validation, API conformance testing and design space explorations infeasible. Our approach builds Random Forest regression model analyze DirectX 3D workload behavior executed software rasterizer, which we have extended with characterizer collect further information via program...
This paper presents a predictive modeling framework for GPU performance. The key innovation underlying this approach is that performance statistics collected from representative workloads running on current generation GPUs can effectively predict the of next-generation GPUs. useful when simulators are available device, but simulation times exorbitant, rendering early design space exploration microarchitectural parameters and other features infeasible. When predicting across three Intel...
Synthesis of digital microfluidic biochips (DMFBs) is a crucial to the advancement and realization miniaturized, automated, programmable biochemistry solutions; synthesis performed in three steps: scheduling, placement routing. In principle, algorithms for specific steps should be interchangeable with one another; however, different research groups typically develop each step isolation from another. Thus, it difficult compare against another, or determine which share synergies. We introduce...
We introduce a Force-directed List Scheduling (FDLS) algorithm for resource-constrained assay compilation targeting Digital Microfluidic Biochips (DMFBs). This has been used in the past high-level synthesis of digital signal processing systems, and is now applied to DMFB synthesis. The results show improvements compared (LS) Path (PS), most efficient heuristics that have proposed, date, DMFBs. FDLS was also competitive with longer-running iterative improvement scheduling algorithms based on...
This paper introduces a predictive modeling framework for GPU performance. The key innovation underlying this approach is that performance statistics collected from representative workloads running on current generation GPUs can effectively predict the of next-generation GPUs. useful when simulators are available device, but simulation times exorbitant, rendering early design space exploration microarchitectural parameters and other features infeasible. When predicting across three Intel...
The authors in this article present a novel similarity-based technique that clusters similar flows, achieving high speedups without compromising accuracy.