A5044401516- Quantum and electron transport phenomena
- Advancements in Semiconductor Devices and Circuit Design
- Quantum Computing Algorithms and Architecture
- Advanced Memory and Neural Computing
- Semiconductor materials and devices
- Analog and Mixed-Signal Circuit Design
- Radio Frequency Integrated Circuit Design
- Neuroscience and Neural Engineering
- Sensor Technology and Measurement Systems
- Advanced MEMS and NEMS Technologies
- Silicon Carbide Semiconductor Technologies
- Muscle activation and electromyography studies
- EEG and Brain-Computer Interfaces
- Neural Networks and Applications
- Quantum-Dot Cellular Automata
- Quantum Information and Cryptography
ETH Zurich
2022-2024
Delft University of Technology
2016-2018
A fault-tolerant quantum computer with millions of bits (qubits) requires massive yet very precise control electronics for the manipulation and readout individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows closer system integration, thus promising a scalable solution enable future computers. In this paper, is proposed, along required specifications, interface classical processor. To prove advantages such system, functionality key circuit blocks...
Cryogenic CMOS, or cryo-CMOS circuits and systems, are emerging in VLSI design for many applications, primis quantum computing. Fault-tolerant bits (qubits) surface code configurations, one of the most accepted implementations computing, operate deep sub-Kelvin regime require scalable classical control circuits. In this paper we advocate need a new generation deep-submicron CMOS operating at deep-cryogenic temperatures to achieve performance required fault-tolerant qubit system. We outline...
Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16-μm 40-nm) are presented in this paper. Several devices from both were extensively characterized at temperatures 4 K below. Based on a detailed understanding the device physics deep-cryogenic temperatures, compact model based MOS11 PSP was developed. In addition to reproducing dc characteristics, accuracy validity models demonstrated by comparing time- frequency-domain simulations complex circuits, such as...
Quantum computing holds the promise to achieve unprecedented computation power and solve problems today intractable. State-of-the-art quantum processors consist of arrays bits (qubits) operating at a very low base temperature, typically few tens mK, as shown in Fig. 15.5.1 The qubit states degrade naturally after certain time, upon loss coherence. For proper operation, an error-correcting loop must be implemented by classical controller, which, addition handling execution algorithm, reads...
Quantum computers1 could revolutionize computing in a profound way due to the massive speedup they promise. A quantum computer comprises cryogenic processor and classical electronic controller. When scaling up at least few thousands, possibly millions, of qubits required for any practical algorithm, CMOS (cryo-CMOS) electronics is allow feasible compact interconnections between controller processor. Cryo-CMOS leverages fabrication infrastructure while exploiting continuous improvement...
The characterization of nanometer CMOS transistors different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard technologies (40 nm 160 nm). A detailed understanding the device physics those was developed captured in an augmented MOS11/PSP model. accuracy proposed model demonstrated by matching simulations measurements DC time-domain 4 and, first time, mK.
Quantum computers could efficiently solve problems that are intractable by today's computers, thus offering the possibility to radically change entire industries and revolutionize our lives. A quantum computer comprises a processor operating at cryogenic temperature an electronic interface for its control, which is currently implemented room few qubits available today. However, this approach becomes impractical as number of grows towards tens thousands required complex algorithms with...
This letter presents an area-efficient and PVT-insensitive segmented duty-cycled resistor (SDR) intended for neural recording amplifiers. The feedback of the capacitively coupled low-noise amplifier is realized with segmentation polysilicon supplementary switches in between. proposed SDR suppresses impedance reduction due to switching resistor's parasitic capacitance. It ensures higher than 1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This paper presents an impedance-boosted analog front-end (AFE) for mm-scale ultra-low power sensor nodes. The proposed AFE employs a discrete-time low noise amplifier (LNA) based on noise-efficient switched-capacitor stages. input impedance, ZIN, is boosted through 27-step multiphase soft-charging technique of the bottom-plate capaci-tance, achieving ZIN > 10 MΩ at 4.5 MHz sampling frequency. LNA achieves 0.4 NEF and 0.15 PEF, smallest values reported to date, while consuming 0.28 μW.
This paper presents a neural interface that senses the electrical double layer (EDL) capacitance as function of ion concentration produced by neurons firing action potentials (AP). Unlike conventional microelectrode arrays (MEAs) detecting voltage, sensing allows access to multiple recording sites with single wire using code-division multiplexing (CDM), thereby significantly reducing number required interconnects. In this work, we implemented 32 drivers and analog front-end circuits (AFEs)...
This paper proposes a segmented duty-cycled resistor (SDR) that replaces the pseudo-resistor for neural recording amplifiers. To authors' best knowledge, proposed design, first time, achieves higher than 1 TΩ resistance and switching frequency above signal bandwidth at same time. Therefore, it eliminates in-band artifacts output DC drift. The SDR up to 1.18TΩ with only 6.5% temperature variation 1.5% chip-to-chip among 10 samples. Hence offers sufficiently low stable cut-off frequencies both...