This paper proposes the first feed-forward equalizing transmitter (Tx) which adaptively relaxes impedance matching. Using an on-chip time-domain reflectometer monitor, Tx accurately detects impedances of channel and receiver (Rx), then automatically configures its termination to maximize received signal by optimally relaxing constraint matching at cost a negligible penalty in integrity. The is universally compatible with arbitrary channels Rxs, achieves better performance power efficiency...

Compact transceivers (TRXs) for highly reflective (HR) interconnects are strongly demanded by the memory industry. Although discontinuous channels like multi-drop DRAM interfaces less suitable high data rates than continuous point-to-point channels, their great advantages in capacity, throughput, and low latency attract market [1-3]. However, compact TRXs low-loss HR more challenging high-loss low-reflection (LR) channels. long-tail ISI of a LR channel can be cost-efficiently canceled an FFE...

For the first time, we prove that 7.8-Gb/s single-ended signaling through a highly reflective channel is feasible at low energy cost by an energy-efficient many-tap decision feedback equalization (DFE) receiver (RX). The reported data rate of 7.8 Gb/s fastest has been achieved more than five taps postcursor intersymbol interference. Compared with prior arts, target multidrop most in-band notches: ten notches. To compensate for large reflection many notches, RX exploits DFE largest tap count...

This article presents a 20-Gb/s/pin 0.0024-mm2 single-ended data-embedded clock signaling (DECS) transceiver (TRX) for short-reach on-chip links. The receiver (RX) directly recovers (self-slicing) and deserializes (auto-deserialization) the data from DECS input of RX front-end without recovery (CDR) or alignment (CDA) circuits, while improving timing requirement tolerance to duty cycle error supply noise. At 20 Gb/s/pin, horizontal eye was measured 0.99 UI at nominal remained equal larger...

This paper presents a 4-tap coefficient-error-robust feed-forward equalization (FFE) transmitter (TX) for massively parallel links. Recently, links such as on-chip [1-3], silicon interposers [4,5], or wide I/Os [6] are gaining popularity to meet increasing demand data transmission with limited power budget. However, calibration overhead thousands compensate coefficient errors due nano-scale variation has high hardware cost. To reduce this overhead, we develop FFE (B-FFE) TX architecture that...

An FFE TX which automatically adapts impedance to arbitrary channel and RX impedances is proposed. Based on on-chip TDR monitoring, the matching adaptively relaxed without increasing reflection. In experiment, proposed adapted any combination of 35-75Ω channels 30-200Ω impedances, achieving 3.8x eye improvement maximum data rate 12Gb/s.

In this research, an one selector-one ReRAM (1S1R) cross-point array of a multi-level cell (MLC) was demonstrated and investigated. To expand high-density feasibility array, MLC pulse writing reading operations were assessed with parasitic line resistances capacitances using Matlab HSPICE simulations. We observed switching energy is important parameter for in actual the operating point view. addition, not only but also selector characteristics are highly device Therefore, study serves power...

This paper proposes a new feed-forward equalizing (FFE) transmitter (Tx) for massively parallel I/Os to reduce calibration circuits and save power consumption. The proposed FFE Tx improves its robustness coefficient error efficiency by utilizing high-pass digital difference filter channel loss attenuate the effects of errors. To verify architecture, we fabricated conventional FFEs in 65 nm CMOS technology tested eye sensitivity variation at 8 Gb/s on 25 dB, 13.2 9.6 dB PCB traces. Compared...

This paper presents an automatic resistive random access memory (ReRAM) SPICE model generator, which enables fast ReRAM circuit evaluation with standard SPICE. Our generator automatically produces models of devices and selectors from the measured I-V data to reduce too much time consumption in manual development for simulation target circuits. To verify our method, diverse ReRAMs were generated simulated various The results show that can accurately describe original allows quantitative...

This paper reports a 50 Mb/s full human body communication (HBC) transceiver (TRX) that communicates through 75 cm channel moving at speed of 0.75 cycle/sec. For the first time, adaptive decision feedback equalization (DFE) and clock data recovery (CDR) were integrated in HBC TRX to adapt real time. In proposed design, transmitter (TX) consists inverter-based driver transmits non-return-to-zero (NRZ) signal body. The receiver (RX) utilized 10-tap DFE compensate for time-varying inter symbol...

This paper presents a phase-difference-modulation transceiver with simple clock recovery for highly-reflective interconnects. By greatly suppressing reflective intersymbol interferences two new enabling mechanisms, phase- difference modulation enables high-speed data communication through multi-drop channels without utilizing decision feedback equalization. A systematic analytical approach is presented, and provides guidelines on how to determine channel signaling parameters exploit the...

This paper proposes a technique to reduce the sample number of channel's pulse response required optimize equalization coefficients. In our method, is aliased in calculating coefficients reducing samples frequency response. As result, computation time acquire greatly reduced. To demonstrate are calculated using conventional and methods then compared. Since necessary reduced by 8 times at most up 7.01 times. For accuracy verification, we also equalized eye sizes both methods. The almost...

In massively parallel short-reach (SR) interfaces [2]–[5], thousands of I/Os communicate through many low-loss interconnects (Fig. 28.7.1). Due to the large number I/Os, each transceiver (TRX) design must fit within a small area and be energy-efficient. One challenge in TRX is increasing clocking power. Distributing clock while satisfying stringent duty cycle constraints, requires duty-cycle correction (DCC) detection (DCD) circuits. For reliable data recovery with reduced eye opening, RXs...

This paper proposes a technique to reduce the sample number of channel's pulse response required optimize equalization coefficients. In our method, is aliased in calculating coefficients reducing samples frequency response. As result, computation time acquire greatly reduced. To demonstrate are calculated using conventional and methods then compared. Since necessary reduced by 8 times at most up 7.01 times. For accuracy verification, we also equalized eye sizes both methods. The almost...

This paper proposes a cost-efficient and automatic method for large data acquisition from test chip without expensive equipment to characterize random process variation in an integrated circuit. Our requires only chip, personal computer, cheap digital-to-analog converter, controller multimeters, thus volume measurement can be performed on office desk at low cost. To demonstrate the proposed method, we designed with current model logic driver array of 128 mirrors that mimic

This brief presents a phase-difference modulation signaling enhanced by decision feedback equalization for multi-drop memory interfaces. The enables efficient data communication via channel, but only if the stub lengths are specially engineered. In this brief, is combined with to extend applicable channel range. A test chip phase-difference-modulation transmitter and receiver was fabricated in 65-nm CMOS technology. With 2-tap equalization, achieved rate of 7.8 Gb/s/pin both channels long...