A5013360615- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and devices
- Parallel Computing and Optimization Techniques
- Neural Networks and Reservoir Computing
- Photonic and Optical Devices
- VLSI and Analog Circuit Testing
- CCD and CMOS Imaging Sensors
- Neuroscience and Neural Engineering
- Radio Frequency Integrated Circuit Design
- Magnetic properties of thin films
- Advanced Graph Neural Networks
- Advanced Data Storage Technologies
- Electrowetting and Microfluidic Technologies
- Cell Image Analysis Techniques
- Analog and Mixed-Signal Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- Neural Networks and Applications
- Advanced Neural Network Applications
Southeast University
2021-2025
SRAM-based computing-in-memory (SRAM-CIM) has been intensively studied and developed to improve the energy area efficiency of AI devices. SRAM-CIMs have effectively implemented high integer (INT) precision multiply-and-accumulate (MAC) operations inference accuracy various image classification tasks [1]–[3],[5],[6]. To realize more complex tasks, such as detection segmentation, support on-chip training for better accuracy, floating-point MAC (FP-MAC) with high-energy are required. However,...
SRAM-based computation-in-memory (CIM) has shown great potential in improving the energy efficiency of edge-AI devices. Most CIM work [3–4] is targeted at MAC operations with a higher input (IN), weight (W) and output (OUT) precision, which suitable for standard-convolution layers fully-connected layers. Edge-AI neural networks tradeoff inference accuracy network parameters. Depthwise (DW) convolution support essential many light-CNN models, such as MobileNet-V2. However, when applying...
SRAM-based computing-in-memory (CIM) has made significant progress in improving the energy efficiency (EF) of neural operators, specifically MAC, used AI applications. Prior CIM methods have demonstrated attractive efficiencies under a fixed/less accumulation length, sparsity, toggle rate, and bit precision [1] –[6]. Analog CIMs (ACIM) offer potentially higher EF but are susceptible to PVT variations. On other hand, digital (DCIM) robust provide moderate efficiency. In prior weight-wise-cut...
With the rapid advancement of artificial intelligence (AI), computing-in-memory (CIM) structure is proposed to improve energy efficiency (EF). However, previous CIMs often rely on INT8 data types, which pose challenges when addressing more complex networks, larger datasets, and increasingly intricate tasks. This work presents a double-bit 6T static random-access memory (SRAM)-based floating-point CIM macro using: 1) cell array with double-bitcells (DBcells) computing units (FCUs) throughput...
Graph convolutional neural networks (GCNs) are for graph structures with large vertex features [1]. GCNs have two phases: aggregation and combination. During the combination phase, matrix multiplications performed using trained weights aggregated features. The however, requires traversing to gather from neighboring vertices. However, performing on graphs high irregularity sparsity presents challenges in terms of memory bandwidth utilization. SRAM computing-in-memory (CIM) can address this...
Spiking-Neural-Networks (SNN) have natural advantages in high-speed signal processing and big data operation. However, due to the complex implementation of synaptic arrays, SNN based accelerators may face low area utilization high energy consumption. Computing-In-Memory (CIM) shows great potential performing intensive efficient computations. In this work, we proposed a JOT-SRAM Spiking-Neural-Network-In-Memory architecture (SNNIM) with 28nm CMOS technology node. A compact bit-cell was...
Artificial Intelligence (AI) processors commonly use deep-learning-based neural networks (DNN), which mainly include convolution layers and fully connected (FC) layers. Both the FC require highly parallel multiply-and-accumulate (MAC) operations generate a great deal of intermediate data. Under von Neumann computing architecture, data transfer between processor memory imposes high energy consumption long latency, significantly deteriorates system's performance efficiency....
Compute-in-memory (CIM) has been widely explored to overcome "Von-Neumann bottleneck" for its high throughput and energy efficiency. However, recent compute-in-memory works can only support integer (INT)-type multiply-and-accumulate (MAC) operations. Floating point MACs (FP-MAC) are highly required achieve both performance training accuracy inference. In this paper, we proposed a ShareFloat CIM architecture which FP-MAC Neural networks with MAC almost the same as that FP64 MAC. A 28nm 64Kb...
Computing-in-memory (CIM) has been proven to achieve high energy efficiency and significant acceleration effects on neural networks with computational parallelism. Based typical integer CIMs, some floating-point CIMs (FP-CIM) are proposed recently execute more accuracy-demanding tasks such as training high-precision inference. However, prior research not adequately explored the relationship between circuit design within FP-CIM architecture hardware/software metrics. Furthermore, in digital...
Computing-in-memory (CIM) has been proved to perform high energy efficiency and significant acceleration effect for computational parallelism neural networks. Floating-point numbers floating-point CIMs (FP-CIM) are required execute performance training accuracy inference However, none of former works discuss the relationship between circuit design based on FP-CIM architecture In this paper, we propose a quantization model figure out in PYTORCH. According experimental results summarize some...
Transformer model has achieved excellent results in many fields, owing of its huge data volume and high precision requirements, the traditional analog compute-in-memory circuit can no longer meet needs. To solve this dilemma, paper proposes a digital based on improved Booth algorithm. The 6T SRAM array stores multiplicand, multiplier is encoded by booth encoder, then, local computing cell (LCC) read corresponding value from according to encoding result. These values are finally sent...
In Paper 7.1, National Tsing Hua University introduces the first true floating-point hybrid-domain (analog & digital) SRAM CIM macro with 16.2 -70.2TFLOPS/W in 22nm.
Abstract The realization of computing in memory based on SRAM(SRAM-CIM) can be divided into three domains: analog domain (AD-CIM), time (TD-CIM), and digital (DD-CIM). However, there exist corresponding disadvantages to the above methods. For AD-CIM, calculation accuracy is poor. Moreover, output stability TD-CIM limited. With a large overhead area, layout wiring DD-CIM are complicated. Aiming solve shortcomings, this paper proposes spike-domain circuit pulse edge counting scheme. uses logic...