A5083331398- Numerical Methods and Algorithms
- Digital Filter Design and Implementation
- Electromagnetic Compatibility and Noise Suppression
- Advanced DC-DC Converters
- Silicon Carbide Semiconductor Technologies
- Model Reduction and Neural Networks
- Low-power high-performance VLSI design
- Parallel Computing and Optimization Techniques
- Neural Networks and Applications
- Advanced Battery Technologies Research
- Evolutionary Algorithms and Applications
- HVDC Systems and Fault Protection
- Matrix Theory and Algorithms
- Induction Heating and Inverter Technology
- Advanced Adaptive Filtering Techniques
- Multilevel Inverters and Converters
- Iterative Methods for Nonlinear Equations
- Advanced Wireless Communication Techniques
- Chaos-based Image/Signal Encryption
- Process Optimization and Integration
- Microgrid Control and Optimization
- Analog and Mixed-Signal Circuit Design
- Power Line Communications and Noise
- Advanced Optimization Algorithms Research
- Mathematical functions and polynomials
Halmstad University
2014-2017
Lund University
2008-2011
General Motors (United States)
2004
Virginia Tech
2002-2004
This paper presents hardware implementations of Taylor series. The focus will be on the exponential function but methodology is applicable any unary function. Two different architectures are investigated, one, original, straight forward and one modified structure. outcomes higher performance, lower area, power consumption for architecture compared to original.
This paper presents an approach to continuous variable design optimization of a power electronics converter. The objective the is minimize total component cost. methodology illustrated with boost factor correction front-end converter input electromagnetic interference filter. system variables are first identified. relevant responses and costs then expressed as function these variables. Finally, by using mathematical techniques, values that cost obtained, given practical constraints on responses.
This article present GA-based design approach to optimization of power electronics circuits is shown be a very effective and powerful tool for obtaining improved solutions compared traditional procedures. In the GA procedure, each represented using "gene string" converter problem, gene string used represent set electrical components that define one possible design. The systems involves large number variables application knowledge from several different engineering fields.
This paper presents a software tool for designing low-cost boost power factor correction front-end converter with an input electromagnetic interference filter. A genetic algorithm based discrete optimizer is used to obtain the design. detailed and experimentally validated model of system, including second order effects, considered. graphical user interface managing design specifications system component databases, controlling monitoring optimization process, analyzing performance top designs...
High performance implementations of unary functions are important in many applications e.g. the wireless communication area. This paper shows development and VLSI implementation like logarithmic exponential function, by using a novel approximation methodology based on parabolic synthesis, which is compared to well known CORDIC algorithm. Both designs synthesized implemented an FPGA as ASIC. The results such with metrics architecture shown exceed factor 4.2, 65 nm Standard-V <sub...
This paper introduces a parabolic synthesis methodology for implementation of approximations unary functions like trigonometric and logarithms, which are specialized efficient hardware mapped VLSI design. The advantages with the are, short critical path, fast computation high throughput enabled by degree architectural parallelism. feasibility is shown developing an approximation sine function in hardware.
This paper presents a procedural approach to the design optimization of boost power factor correction front-end converter with an input EMI filter. The system variables are first identified. relevant responses and component costs then expressed as function these variables. Finally, by using mathematical techniques, variable values that minimize total cost obtained, given practical constraints on responses.
This paper proposes a novel method for performing division on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The is based an inverter, implemented as combination of Parabolic Synthesis and second-degree interpolation, followed by multiplier. It with without pipeline stages individually synthesized while targeting Xilinx Ultrascale FPGA. implementations show better resource usage latency results when compared to other different methods. In case throughput,...
This paper introduces a parabolic synthesis methodology for developing approximations of unary functions like trigonometric and logarithms which are specialized efficient hardware mapped VLSI design. The advantages with the are, short critical path, fast computation high throughput enabled by degree architectural parallelism. feasibility is shown an approximation sine function implementation in hardware.
The need to provide power factor correction (PFC) and low electromagnetic interference (EMI) is required in a growing number of applications. boost PFC circuit widely used fulfil this requirement because it can easily be implemented high with efficiency. aim work insight into the tradeoffs between reducing EMI noise levels penalties, or advantages, incurred thermal performance circuit. A 1 kW converter 230 V AC 50 Hz input 368 output has been constructed for study.
This paper describes the development of an average model a hexagon transformer and rectifier (hex t/r) system. The is derived in dq0 rotating reference frame. A technique for representing commutation inductance located on DC side also presented. Parameter estimation incorporated through use polynomial fits. reduces computation time by factor 5. Experimental results 11 kVA hex t/r prototype are provided to verify validity model.
Computing Euclidean Distances is a very important operation in digital communication, especially the case of trellis coded modulation, where it used numerously. This paper shows that substantial reduction complexity can be achieved hardware processing elements for computing Distances. A down to 39% shown compared traditional designs. The also optimized design done completely ripple free, which leads critical path far more than half. power consumption. free lower consumption two reasons:...
The Harmonized Parabolic Synthesis methodology is a further development of the for approximation unary functions such as trigonometric functions, logarithms and square root with moderate accuracy ASIC implementation. These are extensively used in computer graphics, communication systems many other application areas. For these high-speed applications, software solutions not sufficient, hardware implementation therefore needed. has two outstanding advantages: it parallel, thus reducing...
This paper shows a novel methodology to improve unrolled CORDIC architectures. The is based on removing adder stages starting from the first stage. As an example, 19-stage used but applicable CORDICs with arbitrary number of stages. implemented, simulated, and synthesized into hardware. In paper, performance shown be increased by 23% that dynamic power can reduced 27%.