Jong-Gyu Park

ORCID: 0000-0003-4850-2272
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Research Areas
  • Advanced DC-DC Converters
  • Multilevel Inverters and Converters
  • 3D IC and TSV technologies
  • Electromagnetic Compatibility and Noise Suppression
  • Software-Defined Networks and 5G
  • Marine and Coastal Research
  • Advanced Optical Network Technologies
  • Microgrid Control and Optimization
  • Silicon Carbide Semiconductor Technologies
  • Carbon Nanotubes in Composites
  • Control Systems in Engineering
  • Network Time Synchronization Technologies
  • Hydraulic and Pneumatic Systems
  • Advanced Data Processing Techniques
  • Embedded Systems Design Techniques
  • Fuzzy Logic and Control Systems
  • Technology and Data Analysis
  • Real-Time Systems Scheduling
  • Metallurgy and Material Science
  • Electrostatic Discharge in Electronics
  • VLSI and FPGA Design Techniques
  • Electromagnetic Compatibility and Measurements
  • Scheduling and Optimization Algorithms
  • Advanced Algorithms and Applications
  • Full-Duplex Wireless Communications

Samsung (South Korea)
2005-2023

Kyung Hee University
2020

Pusan National University
2017

Gyeongnam Provincial Namhae College
2011

Gyeongsang National University
2005-2011

Agency for Defense Development
2008

Yonsei University
2002

The windup phenomenon appears and results in performance degradation when the proportional-integral-derivative (PID) controller output is saturated. Integral analyzed on PI plane, a new anti-windup PID proposed to improve control of variable-speed motor drives experimentally applied speed vector-controlled induction driven by pulse width-modulated voltage source inverter. steady-state value integral state predicted while saturated, this utilized as an initial begins operate linear range....

10.1109/tie.2011.2163911 article EN IEEE Transactions on Industrial Electronics 2011-08-15

10.6113/jpe.2011.11.1.045 article EN Journal of Power Electronics 2011-01-20

In this article, we first propose and demonstrate a novel target-impedance (Z) extraction based optimal power distribution network (PDN) design methodology for high performance solid-state-drive (SSD) products. Instead of using the current profile chip models (CPMs), suggested uses both measured spectra hierarchical PDN-Z target-Z calculation. We successfully PCB-level consumed by memory package on SSD device test interposer specifically designed probing without interrupting normal...

10.1109/tsipi.2023.3235310 article EN IEEE Transactions on Signal and Power Integrity 2023-01-01

Abstract This paper presents the generalized and explicit expressions for evaluating performance of multi-phase interleaved converters, such as conversion ratio, efficiency ripples input inductor currents. Especially, output voltage ripple is analysed in depth. Furthermore, transfer functions interest are presented dynamic characteristics analysed. The analysis converter verified through experimental simulation results. Acknowledgment work was supported by University IT Research Center...

10.1080/00207210412331332943 article EN International Journal of Electronics 2005-01-01

This paper, for the first time, proposes a pulse amplitude modulation-4 (PAM-4) based peripheral component interconnect express (PCIe) 6.0 channel design optimization method using Bayesian Optimization (BO). The proposed provides sub-optimal with PAM-4 signaling that maximizes target function considering signal integrity (SI). We formulate of BO as linear combination insertion loss (IL) and crosstalk (FEXT, NEXT) characteristics signaling. To consider trade-off between in signaling, we...

10.1109/epeps51341.2021.9609213 article EN 2021-10-17

E1.S is the family of Enterprise and Data Center Standard Form Factor (EDSFF) for NVMe Solid-State Drive (SSD), providing higher capacities performance as well improved power/thermal solution compared to conventional M.2 SSDs. Due its spatial limitation high density NAND packages other electrical components, however, BGA-type in enclosure-type SSD suffer from low thermal cycle reliability induced by creep solder joint, especially case near physical constraints like screw joints. In this...

10.1109/eurosime56861.2023.10100844 article EN 2023-04-17

Autonomous vessels have been given interesting research topics in both the maritime area and control engineering field with increasingly numerous applications. The practical system is impacted by a vast range of uncertainties, including high nonlinearities dynamic model, variable working environments, influences ocean currents, waves, wind. These factors give big challenges for control, especially precise trajectory tracking control. In this research, new stage adaptive neural network...

10.23919/iccas50221.2020.9268371 article EN 2020-10-13

The present study relates to the acquisition of optimal design and reliability enhancement technology using new solder paste material in development process products order enter SSD market with rapid customer response. As SAC is reduced about 70°C, able reduce power cost, CO2 emissions (35%), PCB/Substrate warpage 50%. Based on these advantages, wants lead a industry change are hoping for generalization application LTS material. In general, package causes failure due at high low temperature...

10.1109/eurosime56861.2023.10100767 article EN 2023-04-17

In this paper, we first propose a methodology to predict Power Supply Noise Induced Jitter (PSIJ) by accurately measuring Sensitivity Function (JSF) and (PSN) at PCB-level then converting them into on-chip level characteristics, respectively for PCIe (Peripheral Component Interconnect Express) Gen5 SSD host serial interface design. As result, successfully obtained JSF PSN from 1 MHz 100 which is targeting frequency range estimate PSIJ caused off-chip noise sources in the device.

10.1109/epeps58208.2023.10314905 article EN 2023-10-15

In this paper, we proposed imitation learning-based equalizer design optimization method on PCIe 6.0. With each update of PCIe, the scheme has evolved to compensate for channel loss. However, due increasing number parameters and their inter-coupling, co-optimizing these becomes essential. While various methods have been researched optimize parameters, they often require re-optimization different conditions or inefficiently train DNN policy used optimization. contrast, our utilizes learning...

10.1109/edaps58880.2023.10468321 article EN 2023-12-12

A Dual-Path Ethernet Module(DPEM) is developed to improve Local Area Network (LAN)'s performance, High Availability(H/A) and security. Since a DPEM simply locates at the front end of any network device as transparent add-on, it does not require sophisticated server reconfiguration. Our evaluation results show that scheme more efficient than conventional LAN structures in various aspects.

10.5302/j.icros.2002.8.3.264 article EN Journal of Control Automation and Systems Engineering 2002-03-01

단상 벅-부스트 DC-AC 인버터는 2개의 DC-DC 컨버터로 이루어져 있다. 두 컨버터는 180[°]의 위상차를 가지는 DC 바이어스된 정현파 기준 전압에 의해 구동된다. 교류로 출력되는 인버터의 최대값은 직류 입력전압 크기에 제약을 받지 않아 입력 직류전원보다 높은 교류 출력전압을 만들 수 본 논문에서는 DC-AC인버터를 설계하고, 프로토타입을 제작하여 실험한다. 전압과 전류 제어기는 마이크로컨트롤러를 이용한 디지털 제어기로 구현된다.

10.5207/jieie.2009.23.10.045 article KO Journal of the Korean Institute of Illuminating and Electrical Installation Engineers 2009-10-31

In this paper, we examine the signal-to-interference-plus-noise ratio (SINR) enhancement by using an antenna diversity technique in 1X-EVDO system. The experiments have been made with two dipoles a lossy cylinder reverberation chamber. interesting frequency range was between 1750 and 1870 MHz. SINR of for minimum mean square error (MMSE) combining shows significant improvement compared to one dipole.

10.1109/aps.2005.1552292 article EN 2006 IEEE Antennas and Propagation Society International Symposium 2005-12-13
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