Bingyi Li

ORCID: 0009-0001-9966-9876
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Research Areas
  • Advanced SAR Imaging Techniques
  • Synthetic Aperture Radar (SAR) Applications and Techniques
  • Geophysical Methods and Applications
  • Antenna Design and Optimization
  • Radio Astronomy Observations and Technology
  • Optical Systems and Laser Technology
  • Radiation Effects in Electronics
  • VLSI and Analog Circuit Testing
  • Low-power high-performance VLSI design
  • Advanced Optical Imaging Technologies
  • Earthquake Detection and Analysis
  • Orbital Angular Momentum in Optics
  • Radar Systems and Signal Processing
  • Numerical Methods and Algorithms
  • Digital Holography and Microscopy
  • Microwave Imaging and Scattering Analysis
  • Cryptography and Residue Arithmetic
  • Radiation Detection and Scintillator Technologies
  • Geological and Geophysical Studies

Beijing Institute of Radio Metrology and Measurement
2019-2024

Beijing Institute of Technology
2016-2023

Chengdu University of Information Technology
2020

Sichuan University
2020

Beijing Zhenxing Metrology & Measurement Institute
2019

University of Manitoba
2005

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal SAR system design is achieve high processing performance with severe size, weight, power consumption constraints. In this paper, we analyse computational burden commonly used chirp scaling (CS) algorithm. To reduce hardware cost, propose partial...

10.3390/s17071493 article EN cc-by Sensors 2017-06-24

In the realm of real-time spaceborne synthetic aperture radar (SAR) imaging, accurate and swift phase factors calculation (PFC) holds significant importance. This paper introduces an innovative ARM-FPGA hybrid acceleration technique designed to expedite factor computation process SAR imaging. By combing strengths Advanced RISC Machines (ARM) Field-Programmable Gate Array (FPGA), our approach achieves optimal performance. The proposed methodology strategically allocates initial intermediate...

10.1109/jstars.2024.3365464 article EN cc-by-nc-nd IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing 2024-01-01

With the development of satellite load technology and very large-scale integrated (VLSI) circuit technology, on-board real-time synthetic aperture radar (SAR) imaging systems have facilitated rapid response to disasters. A key goal SAR system design is achieve high processing performance under severe size, weight, power consumption constraints. This paper presents a multi-node prototype for processing. We decompose commonly used chirp scaling (CS) algorithm into two parts according computing...

10.3390/s18030725 article EN cc-by Sensors 2018-02-28

This paper introduces an effective parallel processing method to design the on-board SAR (Synthetic Aperture Radar) real time imaging processor using FPGA+DSP based on high-resolution algorithm. The architecture of this is designed analysis algorithm operation characteristics and inherent relationship. In order reduce consumption, pipeline joint applied. addition, system uses a combination floating-point operations fixed-point operations, which not only meets accuracy requirements but also...

10.1109/icsidp47821.2019.9173188 article EN 2019 IEEE International Conference on Signal, Information and Data Processing (ICSIDP) 2019-12-01

With the continuous development of satellite payload and system-on-chip (SoC) technology, spaceborne real-time synthetic aperture radar (SAR) imaging systems play a crucial role in various defense civilian domains, including Earth remote sensing, military reconnaissance, disaster mitigation, resource exploration. However, designing high-performance high-reliability SAR that operate harsh environmental conditions while adhering to strict size, weight, power consumption constraints remains...

10.3390/rs15194739 article EN cc-by Remote Sensing 2023-09-27

Augment of integration and complexity makes VLSI circuits more sensitive to errors. Also, soft errors caused by Single Event Upset (SEU) have become a significant threat modern electronic systems. Therefore, the demand high reliability on systems keeps increasing. Aiming at evaluation fault tolerant very large scale integrated implemented SRAM-based FPGA, an automated injection platform via Internal Configuration Access Port (ICAP) for rapid is presented in this paper. We adopt...

10.1109/fpt.2018.00076 article EN 2018-12-01

In multi-channel synthetic aperture radar (SAR), the azimuth non-uniform sampling tends to result in a large number of virtual point targets, which are not expected. Inverse filter algorithm provides new idea for solving this problem. This way can be abstracted as matrix inversion essence, becomes key factor that affects real-time and accuracy pre-processing. study presents implementation method on field programmable gate array (FPGA), based lower upper triangular (LU) decomposition...

10.1049/joe.2019.0748 article EN cc-by The Journal of Engineering 2019-11-01

The swath of the conventional spaceborne synthetic aperture radar (SAR) is parallel-to-orbit, making it inefficient to observe long curved terrain, like coastlines, railways, etc.. Imaging terrains with terrain matching (TM) a promising technique for efficient data acquisition. key feature employment orientations terrains. This paper reports first demonstration SAR TM imaging LJ2-01 satellite. A 161.7 km imaged an azimuth resolution 0.6 m. main technical contributions are: First, new...

10.1109/tgrs.2024.3430833 article EN cc-by-nc-nd IEEE Transactions on Geoscience and Remote Sensing 2024-01-01

New generation space-borne SAR (synthetic aperture radar) systems require high real-time processing performance and have size, weight power constrains. This paper presents a multi-channel stripmap imaging system implemented on an FPGA platform. In order to reduce design cost, high-level synthesis tool Xilinx Vivado HLS is applied implement the system. FFT algorithms in algorithm use IP cores FPGA, rest customized HLS. The modules designed are optimized packaged as blocks for implementation...

10.1587/elex.15.20180254 article EN IEICE Electronics Express 2018-01-01

Controlling of two-dimensional data is a very critical part in synthetic aperture radar (SAR) imaging systems. This paper presents field-programmable gate array (FGPA)-based Double-Data-Rate three Synchronous Dynamic Random Access Memory (DDR3 SDRAM) controller which can efficiently access arbitrary length points along any one-dimensional direction from position data. To improve the efficiency transposition, address DDR3 obtained by sub-matrix cross-mapping method. A complete SAR system with...

10.1109/hpec.2018.8547533 article EN 2018-09-01

The synthesis of the spherical hologram has been widely investigated in recent years as it enables a large field view both horizontally and vertically. However, there is an important issue long time consumption computer-generated holograms (SCGHs). To address this issue, fast diffraction calculation method proposed for SCGH based on phase compensation (PC). In our method, wavefront recording plane (WRP) near used to record distribution from object plane, difference compensated point-to-point...

10.3390/app10175784 article EN cc-by Applied Sciences 2020-08-21

With the development of synthetic aperture radar (SAR) technologies in recent years, huge amount remote sensing data bring challenges for high-speed transmission and real-time processing. The general platform with GPU, CPU or digital signal processor (DSP) cannot meet requirement short delay low power. Therefore, a field-programmable gate array-digital (FPGA-DSP) SAR imaging accelerate has become solution processing performance lower latency In this study, an effective mapping strategy is...

10.1049/joe.2019.0152 article EN cc-by The Journal of Engineering 2019-10-07

Aiming at the application background of sliding spotlight mode Synthetic Aperture Radar (SAR) imaging processing, this paper builds a System-on-a-Programmable-Chip-based (SoPC-based) SAR verification system, which uses software and hardware collaborative design method to complete algorithm-to-hardware mapping can quickly truly perform in FPGA or ASIC. Finally, we analyzed implementation prototype system results. For generation correlation factors, hierarchically decomposes factor operation...

10.1109/icsidp47821.2019.9173344 article EN 2019 IEEE International Conference on Signal, Information and Data Processing (ICSIDP) 2019-12-01

With the developing of science and technology, microwave remote sensing has been widely applied to many areas production life. Synthetic Aperture Radar (SAR) which can provide high-resolution images, become an important means objective observation surveillance in military civilian fields. This paper based on analysis SAR radar echo data characteristics, using peak clipping quantization complete 8-bit quantification processing 32-bit single precision floating point raw field programmable gate...

10.1109/iscit.2016.7751615 article EN 2016-09-01

For the chirp scaling algorithm of synthetic aperture radar imaging, an efficient transmission a large volume data is indispensable. Prior to there requirement for appropriate pre-processing echo signal by digital down conversion (DDC). The DDC module has remove carrier, having filtering processing and down-sampling processing. No matter what imaging mode chosen, such as stripmap mode, spotlight sliding spotlight, needs whole system are matched setting series configurations about this...

10.1049/joe.2019.0168 article EN cc-by The Journal of Engineering 2019-08-20
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