A5042724051- Interconnection Networks and Systems
- Advancements in Semiconductor Devices and Circuit Design
- Embedded Systems Design Techniques
- VLSI and Analog Circuit Testing
- Low-power high-performance VLSI design
- Analog and Mixed-Signal Circuit Design
- Parallel Computing and Optimization Techniques
- Real-Time Systems Scheduling
- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Experimental Learning in Engineering
- Advanced Memory and Neural Computing
- Advanced Data Processing Techniques
- CCD and CMOS Imaging Sensors
- Industrial Vision Systems and Defect Detection
- Advancements in PLL and VCO Technologies
- Sensor Technology and Measurement Systems
- Engineering Education and Technology
- Distributed systems and fault tolerance
- Semiconductor Lasers and Optical Devices
- Fault Detection and Control Systems
- Advanced Malware Detection Techniques
- Modular Robots and Swarm Intelligence
- Security and Verification in Computing
MIREA - Russian Technological University
2021-2024
Delft University of Technology
2012-2015
University of Amsterdam
2013
Karlsruhe Institute of Technology
2013
Carnegie Mellon University
2013
Hanyang University
2013
Leiden University
2013
National Taiwan University
2013
Synopsys (Switzerland)
2010
Systems on chip (SOC) contain multiple concurrent applications with different time criticality (firm, soft, non real-time). As a result, they are often developed by teams or companies, models of computation (MOC) such as dataflow, Kahn process networks (KPN), time-triggered (TT). SOC functionality and (real-time) performance is verified after all have been integrated. In this paper we propose the CompSOC platform design flows that offers virtual execution per application, to allow...
Objectives. Following the completion of development stages due to transistor scaling (Dennard’s law) and an increased number general-purpose processor cores (limited by Amdahl’s law), further improvements in performance computing systems naturally proceeds stage developing specialized subsystems for performing specific tasks within a limited computational subclass. The such requires both selection relevant high-demand application design techniques achieving desired indicators developed...
As technology scales, the impact of process variation on maximum supported frequency (FMAX) individual cores in a MPSoC becomes more pronounced. Task allocation without variation-aware performance analysis can result significant loss yield, defined as number manufactured chips satisfying application timing requirement. We propose task for real-time streaming applications modeled graphs. Our solutions are primarily based throughput requirement, which is most important requirement many...
As technology scales, the impact of process variation on maximum supported frequency (FMAX) individual cores in a multiprocessor system-on-chip (MPSoC) becomes more pronounced. Task allocation without variation-aware performance analysis can greatly compromise and lead to significant loss yield , defined as percentage manufactured chips satisfying application timing requirement . We propose task for best-effort real-time streaming applications modeled graphs. Our solutions are primarily...
Embedded systems are complex, requiring multi-disciplinary skills for their design. Developing appropriate educational curricula is a non trivial problem. system design requires both theoretical and practical understanding. It common in embedded education to provide laboratory sessions put into practice what learnt from lectures textbooks.
Variability in the manufacturing process results variation maximum supported frequency of individual cores a Multi-Processor System-on-Chip (MPSoC). This needs to be considered when performing statistical timing analysis system-level design. As our first contribution, we present framework estimate probability distribution application throughput (e.g. frames per second video decoding) system with Voltage-Frequency Island (VFI) partitions presence variation. The novelty lies computation...
A new process variation monitoring circuit (PVMC) has been proposed in the paper. The goal is to generate a digital signal/code which (code value) will characterize corner. uses only metal-oxide-semiconductor (MOS) transistors detect of their parameters, or corner by generating signals. Process detected based on parameters n-type MOS transistor, such as threshold voltage, oxide thickness. Proposed circuits' operation method called "dynamic measurement", enables monitor using one type (n-type...
A new simple and versatile PV detection method is proposed that allows detecting MOS transistor's parameters variation. Theoretical analysis simulation results for threshold voltage, mobility, oxide thickness prove the performance of circuit (with basic method). The use only transistors lack reference sources allow obtaining small area high accuracy.
A novel approach for process variation detection (PVD) is proposed. Named "dynamic measurement", the proposed method able to detect corner type. Information on variability represented in digital signal (code). Use of such can exclude necessity use special measurement equipment or embedded test structures (ring oscillators, transistor arrays, etc.) during testing, thereby minimizing evaluation time and cost. The further be improved more detailed information corner/variation. In this paper,...
Scaling CMOS technology into nanometer feature-size nodes has made it practically impossible to precisely control the manufacturing process. This results in variation speed and power consumption of a circuit. As solution process-induced variations, circuits are conventionally implemented with conservative design margins guarantee target frequency each hardware component manufactured multiprocessor chips. approach, referred as worst-case design, considerable circuit upsizing, turn reducing...
In this paper a new approach for on chip compensation of resistor value which can change due to process and temperature variations is presented. There special circuit generates three bits corresponding the variation termination value. The generated connect resistors in parallel series through demultiplexor according bits.
A novel process corner detection circuit has been proposed in current work. The uses only metal-oxide-semiconductor (MOS) transistors to precisely detect corner. Such approach allows reducing circuit's area and consumption. Information on is represented digital form (code), which easily using the signal for both testing compensation of variation (PV) other blocks. can be modified monitor not parameter n-type p-type transistors, but also their combinations.
Modern VLSI designs experience significant temperature change due to variations in workload and ambient conditions. The can cause variation other performance parameters such as power reliability. chips use complex self-calibration techniques adjust design safeguard the chip's operation against fluctuations. Any on-chip system needs a detecting observe of chip at spot interest. This paper describes novel approach on submicron CMOS technology for wide range variation.
A new stable current and voltage generation method is proposed. It allows obtaining operating point under process variation (PV) using well-known self-bias technique. Stability against various corners achieved only one type of transistor as (voltage) generating elements. Owing to its simplicity versatility such small area power consumption. Worst-case Monte-Carlo simulations prove that the generated with aid proposed circuit (method) over PV.
Abstract This article analyses the existing variety of sensors used in robotics and related fields also proposes architecture a heterogeneous computing system designed to analyze data obtained from mobile unmanned platform (MUP). A feature platforms is presence tasks that require significantly different level performance on-board for processing corresponding type. Therefore, adaptation universal systems seems be impractical, compared development specialized with architecture. The solve...