A5061896270- Low-power high-performance VLSI design
- VLSI and FPGA Design Techniques
- VLSI and Analog Circuit Testing
- Advancements in PLL and VCO Technologies
- 3D IC and TSV technologies
- Radio Frequency Integrated Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- Analog and Mixed-Signal Circuit Design
Pohang University of Science and Technology
2022-2024
We propose a speculative divide-and-conquer (SDnC) method that enables optimization of large analog/mixed-signal (AMS) circuit. Because modules AMS circuits strongly interact with neighbor modules, they cannot be optimized individually. Therefore, design parameters all must co-optimized for the global optimization, and thus, space exponentially grows circuit size. Although metaheuristic algorithms can enhance efficiency, handle very due to increased size explore. The proposed utilized (DnC)...
We review the speculative divide-and-conquer (SDnC) optimization method. SDnC method is a highly effective for large analog/mixed-signal (AMS) circuits. As size of circuits grows, previous methods face difficulties due to an exponential increase in design complexity. To reduce complexity, decreases evaluation and levels from AMS circuit smaller module units. This significant reduction complexity could be validated through comparisons with other methods, such as parameter sweep PSO....
We present a fast eye size evaluation method for high speed signal. In order to estimate the smallest quickly, worst data pattern, which maximizes inter-symbol interference (ISI) accumulation, is determined by utilizing pulse response and simulated. The proposed compared with SPICE simulation that utilizes pseudo random bit sequence (PRBS) as an input