A5114803753- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Photonic and Optical Devices
- Semiconductor Lasers and Optical Devices
- Semiconductor materials and devices
- Optical Network Technologies
- Analog and Mixed-Signal Circuit Design
- VLSI and Analog Circuit Testing
- Interconnection Networks and Systems
- Advanced Photonic Communication Systems
- Soil and Unsaturated Flow
- Advanced Fiber Optic Sensors
- Adhesion, Friction, and Surface Interactions
- Landslides and related hazards
- Low-power high-performance VLSI design
- Advanced Data Storage Technologies
- Automotive and Human Injury Biomechanics
- Geophysics and Sensor Technology
- Geophysical Methods and Applications
- Anaerobic Digestion and Biogas Production
- Combustion and Detonation Processes
- Technology and Data Analysis
- Physical Unclonable Functions (PUFs) and Hardware Security
- Software System Performance and Reliability
- Advanced Combustion Engine Technologies
SK Group (South Korea)
2022-2024
Korea University
2017-2024
Dankook University
2023
Korea Advanced Institute of Science and Technology
2020-2023
Pusan National University
2012
With increasing demand for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$50\text{Gb}/\mathrm{S}+$</tex> , transceivers, PAM-4 modulation has become dominant over NRZ [1–5], [7], and multiphase clocking is used to maximize data rate in a given process technology. However, the use of high-resolution phase interpolators (Pls) [1] or xmlns:xlink="http://www.w3.org/1999/xlink">$2\times$</tex> frequency oscillator (OSC) multiple Pls [2] results...
Trajectory prediction for industrial vehicles, such as forklifts, must account complex environments, including load capacity, variations of terrain, and confined spaces. Unlike trajectory pedestrians or personal the trajectories vehicles are influenced by these physical factors, necessitating models that integrate considerations accurate predictions. This study proposes a volume-based method applying prompt engineering to input large language (LLMs). Specifically, includes size bounding box...
A 30-Gb/s three-level pulse amplitude modulation (PAM-3) transceiver is designed with a one-tap tri-level decision feedback equalizer (DFE) to realize high-speed dynamic random access memory (DRAM) interface via the 28-nm CMOS process. 1.5-bit/pin bit efficiency achieved by encoding and decoding 3-bit data in two unit intervals (UIs). The half-rate PAM-3 transmitter modulates single-ended pseudorandom binary sequence (PRBS) 7/15 using low-power logic an output driver. receiver achieves error...
A three-level pulse amplitude modulation (PAM-3) transceiver (TRX) with improved simultaneous switching output (SSO) noise and reference voltage margin was studied. PAM- 3 signaling an insertion of bits in 2-unit intervals (UI) implemented using the upper, under, ground voltages, achieving 150% pin efficiency. The ground-referenced (GRS) charge pump driver reduced SSO maintained as solitary return current path. Capacitive peaking middle edge-rate boosting were for transmitter (TX)...
A 1.3–4-GHz quadrature-phase digital delay-locked loop (DDLL) with sequential delay control and a reconfigurable line is designed using 28 nm CMOS process. The time resolution of the DDLL reduced by updating code sequentially. bidirectional shift register enables this operation low power, resulting in bang-bang jitter that three times smaller than conventional DDLL. Conventional replaced after lock to reduce locking time. wide range achieved line. Unlike DDLL, minimum difference adjustable...
AbstractSince the resilient modulus is changed by suction and moisture conditions in subgrade soils, these effects should be considered model to rationally predict modulus. The stress one of possible parameters for considering influence condition can taken into account In this study, average skeleton was proposed applied on subgrades. predicted compared with experimental data evaluate suitability established models. It found that has an independent effect reasonably estimates soils...
Bandwidths of memory interfaces have been increased tremendously to enable high-data throughput while maintaining single-ended signaling and the supply voltage I/O has scaled down. Due increasing interface bandwidth required area power consumption as well, resulting in higher circuit design costs [3]. A high-loss channel causes ISI, which turn limits maximum data rate. Therefore, complex equalizers are needed for compensation, additional dissipation overhead. As sampling rate increases,...
This article presents a 0.975-pJ/bit 56-Gb/s pulse amplitude modulation-4 (PAM-4) receiver using time-based least significant bit (LSB) decoder in 28-nm CMOS technology. The proposed time-domain decision technique improves the robustness of comparator voltage variations by separating data and reference paths. If difference is constant regardless common-mode shift, achieves low error rate (BER). To improve timing margin LSB from data-dependent jitter, sample-and-hold (S/H) structure adopted...
The bandwidth of parallel DRAM I/O has increased to meet big-data requirements. High memory (HBM) interfaces use up 1024 pins, and with an clock frequency, their power consumption also [1]. Figure 28.5.1 shows four HBM interface approaches. Conventional a termination-less structure at the receiver reduce consumption. For higher data rates receiver-side termination can be used improve signal integrity. However, this causes large static current for long consecutive identical digits (CID)....
This brief presents a 1-tap pre-emphasis transmitter (TX) for single-ended ground-terminated memory interface with 28 nm complementary metal-oxide-semiconductor (CMOS) technology. By employing charge pump scheme, voltage level below ground was used to remove inter-symbol interference (ISI). Encoded the unit interval (UI) delayed data, proposed equalization technique increases vertical margin receiver (RX) compared conventional feed-forward (FFE). In addition, short current after removed, and...
Piceid is widely used in food, cosmetics, and pharmaceuticals because of its therapeutic benefits. However, the use piceid as a drug limited low solubility. To increase solubility, we synthesized glucosides using maltosyltransferase from Caldicellulosiruptor bescii. The MTase gene was cloned expressed Escherichia coli. enzyme had unique transfer specificity to maltosyl units. Four transglycosylation products were present identified by thin-layer chromatography recycling preparative...
In an effort to keep pace with bandwidth growth, DRAM employes the quad data rate (QDR) transfer four in one clock cycle. recent graphic memories, QDR is being implemented by a phase-locked loop (PLL). However, it hard apply PLL main and mobile memories for its high power dissipation hardware cost. Therefore, we propose new delay-locked loop-based quadrature generator (DLL-QCG) replace PLL. A sub-range technique adopted phase interpolator (PI) achieve very fine resolution low small area....
This brief presents a low-power counter-based adaptive equalizer that does not require additional power-hungry comparators for an adaptation loop. A pulse generator in the proposed obviates need error sampling comparators. Instead, it allows receiver to utilize output of data decision comparator by generating indicates whether makes firm incoming data. single is shared recovery path and Consequently, achieves low power dissipation owing reduced number Fabricated 28-nm CMOS technology,...
An important issue in wireline receivers (RX) is minimizing the area and power consumption while overcoming channel attenuation with an equalizer. The greater compensation for loss at analog front end (AFE) of RX, lower number decision feedback equalizer (DFE) taps. Power dissipation can be reduced by reducing DFE This brief presents a technology that compensates proposed AFE based on two-stage continuous-time linear (CTLE), low high bandwidth amplifiers, gain controller. It sufficiently...
In this demonstration, we design the integration of WLAN-based RF transmission and multi-wavelength FSO transmission, achieving 20Gbps. Two wavelength beams 1549.322nm 1550.124nm are modulated used for MQAM OFDM signal by USRP 10Gbps OOK BERT. It is shown that when received optical power greater than –13dBm beams, WDM-FSO system achieves BER requirements WLAN. Furthermore, signal, error-free condition below 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This study presents a wireline pulse amplitude modulation-4 (PAM-4) receiver using the least significant bit (LSB) decoding method that uses offset of comparators. The proposed LSB can generate same output as conventional comparator by effectively adding desired voltage to only one differential PAM-4 signals. Because replaces 4-input with 2-input comparator, it improve error rate (BER) performance much most (MSB). predetermined is useful not for but also direct decision feedback equalizer...
This brief presents a single-ended (SE) receiver (RX) with self-referenced (SR) technique using sample and hold (S&H) circuits. The proposed RX does not require reference voltage (VREF) for data recovery by comparing the present previous data. was implemented as half-rate architecture to halve clock frequency facilitate S&H operation. Moreover, decision feedback equalizer (DFE) is suitable SR improves reliability of eliminating inter-symbol interference (ISI). prototype RX, fabricated 28-nm...
Many Internet of Things (IoT) devices have special and demanding design requirements, including limited energy, size, storage processing capabilities. In addition, many IoT may be deployed in public places, making them vulnerable to physical attacks replication attacks. Therefore, are required provide a solid security against duplication counterfeiting even with these restrictions. To solve this problem, we propose low-power unclonable function (PUF) for IoTs. The proposed PUF at 0.5 V...
A power reduction scheme that uses ac termination at receiver (RX) and a transmitter (TX) output driver with an active inductor part (AIP) is proposed for point-to-point postlow-power mobile DRAM4 interface 8 Gb/s. AC the RX I/O can reduce consumption by preventing dc loss. However, this causes inter symbol interference (ISI), owing to difference in gain depending on frequency. Thus, generates more jitter, which results smaller eye-opening than conventional on-die termination. The AIP TX...
The required data rate of wireline communications has increased; however, channel attenuation limits the bandwidth. Bit-efficient signaling is an effective and efficient solution because more can be transmitted at same Nyquist frequency. Several methods for increasing bit efficiency, such as multi-wire signaling, multi-level symbol correlation schemes, have been proposed. Each scheme generate additional codes by encoding data. Additional used to transmit or embed transitions. In this study,...
This brief presents a phase rotator (PR)-based delay-locked loop (DLL) for dynamic random-access memory interface in 28-nm CMOS technology. A direct input–output comparison using sub-sampling technique reduces the effect of timing mismatch replica delay line synchronizing an input clock and output strobe clock. divided samples alignment. 4-b analog-to-digital converter was used acquisition. The is aligned with respect to sampling bang-bang detector. Two DLLs synchronization are implemented...
Free-space wireless optical communication (FSO), which adopts the wavelength division multiplexing (WDM) technology, transmits and receives various data combinations on a single channel. The mixed wavelengths are separated by WDM demodulation using different refraction of light. Due to chromatic dispersion, phase arriving signal would depend wavelength. Therefore, clock recovery (CDR) is required determine optimum sampling point in FSO-WDM systems. proposed baud-rate CDR uses an integrator...
The increase in GPU-based AI applications, cloud-based gaming, and video streaming services has driven the need for new a graphics memory that operates at higher bandwidth power efficiency than existing GDDR6 SDRAM, leading to introduction of GDDR7 standard [1]. Since performance degradation due thermal throttling, cost, device reliability are major development considerations high-power PAM3 signaling is applied on single-ended pins improve consumption, while maintaining clock frequency [2]....