A5063243279- 3D IC and TSV technologies
- Electronic Packaging and Soldering Technologies
- Advanced MEMS and NEMS Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Nanofabrication and Lithography Techniques
- Acoustic Wave Resonator Technologies
- Photonic and Optical Devices
- Semiconductor materials and devices
- Mechanical and Optical Resonators
- Advanced Surface Polishing Techniques
- Ferroelectric and Negative Capacitance Devices
- Semiconductor Lasers and Optical Devices
- Additive Manufacturing and 3D Printing Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Quantum-Dot Cellular Automata
- Copper Interconnects and Reliability
- Electrical and Thermal Properties of Materials
- Satellite Communication Systems
- VLSI and Analog Circuit Testing
- Antenna Design and Optimization
- Optical Network Technologies
- Electrodeposition and Electroless Coatings
- Photonic Crystals and Applications
- Energy Harvesting in Wireless Networks
- Advancements in PLL and VCO Technologies
IMEC
2013-2024
KU Leuven
2007-2008
High performance 3D integration Systems need a higher interconnect density between the die than traditional μbump interconnects can offer. For ultra-fine pitches below 5μm different solution is required. This paper describes hybrid wafer-to-wafer (W2W) bonding approach that uses Cu damascene patterned surface bonding, allowing to scale down interconnection pitch 5 μm, potentially even 1μm, depending on achievable W2W accuracy. The method referred as since of Cu/dielectric surfaces leads...
The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to CMOS flow with industrially available tools is high interest for the electronics industry because such can produce more compact systems. We present 300mm industry-compliant via-middle TSV module, an advanced high-k/metal gate platform. TSVs are fabricated by Bosch after contact and before first metal layer. target copper diameter 5μm via depth in silicon substrate 50μm. Dense structures have...
We demonstrate a microbump flip-chip integrated 14nm-FinFET CMOS-Silicon Photonics (SiPh) technology platform enabling ultra-low power Optical I/O transceivers with 1.6Tb/s/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> bandwidth density. The transmitter combines differential FinFET driver Si ring modulator, 40Gb/s NRZ optical modulation at 154fJ/bit dynamic consumption in 0.015mm footprint. receiver trans-impedance amplifier (TIA)...
This paper presents a novel electrostatic actuator using fringing fields as the actuation mechanism, i.e. an fringing-field or EFFA. The device is produced on insulating substrate in simple two-mask process involving only one sacrificial layer and metallization. To demonstrate EFFA capabilities, we characterized EFFAs various technological implementations of remarkable simplicity. simplicity allows vast flexibility for processing result strongly eases integration into existing technologies....
Silicon Interposer provides very high density interconnect combining through vias and fine wiring. The concept reported in this paper is implementing integrated power supply layers with decoupling metal insulator capacitor to enhance signal integrity. In addition an upscale damascene process was used fabricate bandwidth routing interconnect. A detailed characterization of the warpage behavior along processing steps electrical interposer TSV BEOL are reported.
We show for the first time that substrate can influence lifetime of capacitive RF MEMS switches. demonstrate should not be ignored. The environment on a switch is different when it fabricated two substrates. also present actuated with DC voltage lower than pull-in after some time. goal performed experiment was to emphasize charging substrate. presented results help understand problem.
This paper discusses dielectric charging in electrostatic RF-MEMS switches. We show that more than one mechanism can be present and impacts their lifetime. These different mechanisms cancel, mitigate or enhance each other’s influence on the lifetime, depending materials used test conditions. Contrarily to common understanding of charging, we charge trapping interposer is not always dominant leading failure. finally bipolar actuation a general remedy for RF MEMS
An analytical model simulating the bowing at wafer or thin die level was applied to imec's 3D interposer technology. The calibration methodology is explained. A good correlation between simulation and measurement has been found different stages during processing. Secondly, a combining all features used simulate induced level. Finally, provide some recommendations mitigate without any drastic change in structure impact onto its performances.
We present a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -thin-profile power delivery solution including charge pump with integrated passives. Targeting 1 W/mm <sup xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> or higher density, 2.5-D high-density metal-insulator-metal (MIM) capacitor deposited on high aspect ratio (HAR) (up to 5) oxide studs is...
The growing demand for I/O bandwidth in highperformance applications, such as datacenter switches and HPC nodes, drives the need on-package integration of Optical modules with host CMOS ICs [1]. Silicon Photonics (SiPh) is a prime technology platform to realize multi-Tb/s hybrid CMOS-SiPh 1m-500m+ optical interconnect distances [2]. Such require interfaces dense, high-speed electrical low-noise power ground delivery, which can be enabled by through-silicon vias (TSV) into SiPh platform....
In this work we present a novel technique to fabricate embedded 3D MIM capacitor on Si interposer showing capacitance densities as high 96 nF/mm2 and low leakage current of 1.5 pA/nF, while having breakdown voltage 10.5 V > 10 years lifetime (T50%@1V, 100 ˚C = 5.18e16 s).
This paper presents a novel electrostatic actuator using fringing fields as actuation mechanism, ie fringing-field or EFFA. The device is produced on an insulating substrate in simple 2-mask process involving only one sacrificial layer and metallisation. As proof of concept, we characterized EFFA-based tuneable RF devices circuits various technological implementations remarkable simplicity. simplicity allows vast flexibility for the processing result strongly eases integration EFFA 's into...
Higher performance, higher operation speed and volume shrinkage require high 3D TSV interconnect densities. This work focuses on a via-middle process flow, which implies processing of the 3D-TSV after front-end-of-line (FEOL) before back-end-of-line (BEOL) process. A description imec 300 mm platform is given, challenges towards reliable integration density aspect-ratio interconnections are also discussed in details.
Memory bandwidth is the main bottleneck to improve performance of today's computing systems, and demand for expected grow exponentially in coming years. The development advanced packaging solutions making use a silicon bridge such as Embedded Multi-Die Interconnect Bridge (EMIB) Fan-Out Wafer Level Package (FO-WLP) are promising achieve high density bring more memory closer units. This work demonstrates 0.3V-swing 7mm long link over bridge, running at bitrate 9Gbps. It achieves 48fJ/bit/mm...
In this article, the reliability assessment of a 2.5-D metal–insulator–metal (MIM) capacitor, built in thicker back-end line layer using 23-nm-thick ALD-deposited Al-doped HfO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_\text{2}$</tex-math> </inline-formula> high- notation="LaTeX">$\kappa$</tex-math> dielectric, is performed time-dependent dielectric breakdown (TDDB) measurements. This compatible with...
Three modifications of the structure a 4 BEOL layers with 10×100μm TSV Si interposer are proposed to mitigate tensile stress and release warpage. By using thicker compressive PMD layer, reducing Metal1 thickness higher oxide build BEOL, bowing contributions TSV, Via2 Metal4 were reduced by 75%, 37% 120% respectively. In total, at wafer level was 75% after full front side processing.