A5101452391- Cloud Computing and Resource Management
- Scientific Computing and Data Management
- Embedded Systems Design Techniques
- GaN-based semiconductor devices and materials
- Parallel Computing and Optimization Techniques
- Graph Theory and Algorithms
- VLSI and Analog Circuit Testing
- Ga2O3 and related materials
- Semiconductor materials and devices
- Interconnection Networks and Systems
- VLSI and FPGA Design Techniques
Peking University
2017-2025
King University
2025
Institute of Microelectronics
2017
Modern commercial Field-Programmable Gate Array (FPGA) architectures support dual-output look-up tables (LUTs). If the number of total inputs in two small LUTs do not exceed constraint, e.g., 5 Xilinx UltraScale+ series, we can pack them into one LUT to reduce area, i.e., LUTs. However, previous works have fully utilized this feature. They usually generate single-output technology mapping phase and merge a later packing phase. In situation, they cannot get merging information during will...
Lower Ti/Al/Ni/Au Ohmic contact resistance on AlGaN/GaN with wider rapid thermal annealing (RTA) temperature window was achieved using recessed structure based self-terminating oxidation assisted wet etching technique (STOAWET), in comparison conventional contacts. Even at lower such as 650°C, by STOAWET could still obtain of 1.97Ω·mm, while mainly featured Schottky contact. Actually, both recess and mesa isolation processes be accomplished one process step the is wide, simplifying HEMT...