Mobility Engineering in Vertical Field Effect Transistors Based on Van der Waals Heterostructures

• DOI: 10.1002/adma.201704435
• Publication Date: 2018-01-15T09:48:37Z
• Authors: Yong Seon Shin; Kiyoung Lee; Young Rae Kim; Hyangsook Lee; I. Min Lee; Won Tae Kang; Boo Heung Lee; Kunnyun Kim; Jinseong Heo; Seongjun Park; Young Hee Lee; Woo Jong Yu
• Keywords: 02 engineering and technology; 0210 nano-technology

Abstract Vertical integration of 2D layered materials to form van der Waals heterostructures (vdWHs) offers new functional electronic and optoelectronic devices. However, the mobility in vertical carrier transport vdWHs field‐effect transistor (VFET) is not yet investigated spite importance for successful application VFETs integrated circuits. Here, VFET under different drain biases, gate metal work functions first engineered. The traps WSe 2 are main source scattering, which influences three distinct mechanisms: Ohmic transport, trap‐limited space‐charge‐limited transport. can be improved by suppressing trap states raising Fermi level . This achieved increasing injected density applying a high voltage, or decreasing Schottky barrier at graphene/WSe metal/WSe junctions bias reducing function, respectively. Consequently, Mn vdWH +50 V voltage about 76 times higher than initial Au vdWH. enables further improvements