A 10-bit 2.5-MS/s SAR ADC with 60.46 dB SNDR in 0.13-μm CMOS technology

• DOI: 10.1007/s10470-014-0318-9
• Publication Date: 2014-05-07T12:02:22Z
• Authors: Ruofan Dai; Yunlong Zheng; Zi Wang; Hongwei Zhu; Weiran Kong; Shichang Zou
• Keywords: Spurious-free dynamic range; Successive approximation ADC; 12-bit; Integral nonlinearity; Differential nonlinearity; Figure of Merit

This paper presents a 10-bit 2.5-MS/s successive-approximation-register (SAR) analog- to-digital-converter (ADC) design for micro controller unit of signal process system. Because of the proposed new segmented architecture of 7 MSBs-plus-3 LSBs capacitor---resistor hybrid digital-to-analog-converter using a thermometer decoder for the most significant 5 MSBs, this design achieves superior static nonlinearity and dynamic performance of SNDR, SFDR. Utilizing the proposed deviation calibration technique, the discharging and charging via substrate resulting from deviation of the comparator's common-mode voltage is cancelled. The ADC is fabricated in a standard 1P5M 0.13-μm CMOS technology. The peak DNL and INL are +0.18/?0.20-LSB, +0.30/?0.25 LSB respectively while the ENOB is 9.52-bit around all process---voltage---temperature corner analysis. At a 2.3-V supply voltage and a 2.5-MS/s sampling rate, the ADC achieves a SNDR of 60.46 dB, SFDR of 75.32 dB while the power dissipation is 0.191-mW, that resulting in a figure of merit of 98.45 fJ/c-s. The die of ADC measures 0.51 × 0.20 mm2 resulting in area efficiency of 122.6 μm2/code and compared with the benchmark SAR ADCs, this work is the most area efficient design.