Ultra-low voltage fractional-order differentiator and integrator topologies: an application for handling noisy ECGs

• DOI: 10.1007/s10470-014-0391-0
• Publication Date: 2014-09-01T13:05:34Z
• Authors: Georgia Tsirimokou; Costas Psychalinos
• Keywords: 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology

Fractional-order differentiator and integrator topologies are introduced in this paper. They offer the benefits of resistorless realizations, electronic adjustment of their characteristics, and capability for operating in 0.5 V power supply voltage. These have been achieved through the employment of the concept of the Sinh-Domain filtering. The performance of the proposed blocks has been evaluated through the Analog Design Environment of the Cadence software, using MOS transistor models provided by the TSMC 180 nm process. As application example, the design of a Sinh-Domain chain for realizing the preprocessing of the Pan-Tomkins algorithm has been given, where the conventional differentiator has been substituted by a fractional-order differentiator.