A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

• DOI: 10.1007/s10836-016-5599-8
• Publication Date: 2016-07-11T02:38:02Z
• Authors: Guillaume Renaud; Manuel J. Barragan; Asma Laraba; Haralampos-G. Str...; Salvador Mir; Hervé Le-Gall; Hervé Naudet
• Keywords: [INFO.INFO-AI] Computer Science [cs]/Artificial Intelligence [cs.AI]; [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics; 02 engineering and technology; [INFO.INFO-IA]Computer Science [cs]/Computer Aided Engineering; [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation; [INFO.INFO-IA] Computer Science [cs]/Computer Aided Engineering; [SPI.TRON] Engineering Sciences [physics]/Electronics; 620; 004; [INFO.INFO-AI]Computer Science [cs]/Artificial Intelligence [cs.AI]; [SPI.TRON]Engineering Sciences [physics]/Electronics; [INFO.INFO-ES] Computer Science [cs]/Embedded Systems; 0202 electrical engineering, electronic engineering, information engineering; [INFO.INFO-ES]Computer Science [cs]/Embedded Systems; [INFO.INFO-MO] Computer Science [cs]/Modeling and Simulation; [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics

This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity characterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the LSB of the target ADC. The proposed ramp generator is employed in a servo-loop configuration to implement a BIST version of the reduced-code linearity test technique for pipeline ADCs, which drastically reduces the volume of test data and, thereby, the test time, as compared to the standard test based on a histogram. The demonstration of the pipeline ADC BIST is carried out based on a mixture of transistor-level and behavioral-level simulations that employ actual production test data.