Microarchitecture of the Godson-2 Processor

• DOI: 10.1007/s11390-005-0243-6
• Publication Date: 2005-04-19T08:09:59Z
• Authors: Wei-Wu Hu; Fu-Xin Zhang; Zu-Song Li
• Keywords: Microarchitecture; Pipeline burst cache; Branch predictor; Speculative execution; Register file

The Godson project is the first attempt to design high performance general-purpose microprocessors in China. This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implements the 64-bit MIPS-like instruction set. The adoption of the aggressive out-of-order execution techniques (such as register mapping, branch prediction, and dynamic scheduling) and cache techniques (such as nonblocking cache, load speculation, dynamic memory disambiguation) helps the Godson-2 processor to achieve high performance even at not so high frequency. The Godson-2 processor has been physically implemented on a 6-metal 0.18µm CMOS technology based on the automatic placing and routing flow with the help of some crafted library cells and macros. The area of the chip is 6,700 micrometers by 6,200 micrometers and the clock cycle at typical corner is 2.3ns.